Refine the macros and definitions by using 'tab' spaces and new
lines wherever necessary. Also refine the comment in
'idpf_ctlq_setup_regs' and remove the TODO comment in idpf_rss_hash
enum as it doesn't make any sense.

Signed-off-by: Pavan Kumar Linga <pavan.kumar.li...@intel.com>
Signed-off-by: Simei Su <simei...@intel.com>
---
 drivers/common/idpf/base/idpf_controlq.c     |  2 +-
 drivers/common/idpf/base/idpf_controlq_api.h | 10 +----
 drivers/common/idpf/base/idpf_lan_pf_regs.h  |  7 +--
 drivers/common/idpf/base/idpf_lan_txrx.h     | 47 +++++++++-----------
 drivers/common/idpf/base/idpf_lan_vf_regs.h  | 25 +++++++----
 5 files changed, 46 insertions(+), 45 deletions(-)

diff --git a/drivers/common/idpf/base/idpf_controlq.c 
b/drivers/common/idpf/base/idpf_controlq.c
index da5c930578..c24bfd23ef 100644
--- a/drivers/common/idpf/base/idpf_controlq.c
+++ b/drivers/common/idpf/base/idpf_controlq.c
@@ -13,7 +13,7 @@ static void
 idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq,
                     struct idpf_ctlq_create_info *q_create_info)
 {
-       /* set head and tail registers in our local struct */
+       /* set control queue registers in our local struct */
        cq->reg.head = q_create_info->reg.head;
        cq->reg.tail = q_create_info->reg.tail;
        cq->reg.len = q_create_info->reg.len;
diff --git a/drivers/common/idpf/base/idpf_controlq_api.h 
b/drivers/common/idpf/base/idpf_controlq_api.h
index 78a54f6b4c..38f5d2df3c 100644
--- a/drivers/common/idpf/base/idpf_controlq_api.h
+++ b/drivers/common/idpf/base/idpf_controlq_api.h
@@ -21,10 +21,7 @@ enum idpf_ctlq_type {
        IDPF_CTLQ_TYPE_RDMA_COMPL       = 7
 };
 
-/*
- * Generic Control Queue Structures
- */
-
+/* Generic Control Queue Structures */
 struct idpf_ctlq_reg {
        /* used for queue tracking */
        u32 head;
@@ -157,10 +154,7 @@ enum idpf_mbx_opc {
        idpf_mbq_opc_send_msg_to_peer_drv       = 0x0804,
 };
 
-/*
- * API supported for control queue management
- */
-
+/* API supported for control queue management */
 /* Will init all required q including default mb.  "q_info" is an array of
  * create_info structs equal to the number of control queues to be created.
  */
diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h 
b/drivers/common/idpf/base/idpf_lan_pf_regs.h
index 8542620e01..e47afad6e9 100644
--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h
@@ -80,10 +80,11 @@
 /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is
  * spacing b/w itrn registers of the same vector.
  */
-#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \
-               ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))
+#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing)                
\
+       ((_reg_start) + ((_ITR) * (_itrn_indx_spacing)))
 /* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */
-#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) 
* 0x1000))
+#define PF_GLINT_ITR(_ITR, _INT)       \
+       (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))
 #define PF_GLINT_ITR_MAX_INDEX         2
 #define PF_GLINT_ITR_INTERVAL_S                0
 #define PF_GLINT_ITR_INTERVAL_M                IDPF_M(0xFFF, 
PF_GLINT_ITR_INTERVAL_S)
diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h 
b/drivers/common/idpf/base/idpf_lan_txrx.h
index 7b03693eb1..4951e266f0 100644
--- a/drivers/common/idpf/base/idpf_lan_txrx.h
+++ b/drivers/common/idpf/base/idpf_lan_txrx.h
@@ -8,9 +8,9 @@
 #include "idpf_osdep.h"
 
 enum idpf_rss_hash {
-       /* Values 0 - 28 are reserved for future use */
-       IDPF_HASH_INVALID               = 0,
-       IDPF_HASH_NONF_UNICAST_IPV4_UDP = 29,
+       IDPF_HASH_INVALID                       = 0,
+       /* Values 1 - 28 are reserved for future use */
+       IDPF_HASH_NONF_UNICAST_IPV4_UDP         = 29,
        IDPF_HASH_NONF_MULTICAST_IPV4_UDP,
        IDPF_HASH_NONF_IPV4_UDP,
        IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK,
@@ -19,7 +19,7 @@ enum idpf_rss_hash {
        IDPF_HASH_NONF_IPV4_OTHER,
        IDPF_HASH_FRAG_IPV4,
        /* Values 37-38 are reserved */
-       IDPF_HASH_NONF_UNICAST_IPV6_UDP = 39,
+       IDPF_HASH_NONF_UNICAST_IPV6_UDP         = 39,
        IDPF_HASH_NONF_MULTICAST_IPV6_UDP,
        IDPF_HASH_NONF_IPV6_UDP,
        IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK,
@@ -32,34 +32,31 @@ enum idpf_rss_hash {
        IDPF_HASH_NONF_FCOE_RX,
        IDPF_HASH_NONF_FCOE_OTHER,
        /* Values 51-62 are reserved */
-       IDPF_HASH_L2_PAYLOAD            = 63,
+       IDPF_HASH_L2_PAYLOAD                    = 63,
+
        IDPF_HASH_MAX
 };
 
 /* Supported RSS offloads */
-#define IDPF_DEFAULT_RSS_HASH ( \
-       BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \
-       BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \
-       BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \
-       BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \
-       BIT_ULL(IDPF_HASH_FRAG_IPV4) | \
-       BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \
-       BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \
-       BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \
-       BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \
-       BIT_ULL(IDPF_HASH_FRAG_IPV6) | \
+#define IDPF_DEFAULT_RSS_HASH                  \
+       (BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) |     \
+       BIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) |     \
+       BIT_ULL(IDPF_HASH_NONF_IPV4_TCP) |      \
+       BIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) |    \
+       BIT_ULL(IDPF_HASH_FRAG_IPV4) |          \
+       BIT_ULL(IDPF_HASH_NONF_IPV6_UDP) |      \
+       BIT_ULL(IDPF_HASH_NONF_IPV6_TCP) |      \
+       BIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) |     \
+       BIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) |    \
+       BIT_ULL(IDPF_HASH_FRAG_IPV6) |          \
        BIT_ULL(IDPF_HASH_L2_PAYLOAD))
 
-       /* TODO: Wrap below comment under internal flag
-        * Below 6 pcktypes are not supported by FVL or older products
-        * They are supported by FPK and future products
-        */
 #define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \
-       BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \
-       BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \
-       BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \
-       BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \
-       BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \
+       BIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) |           \
+       BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) |              \
+       BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) |            \
+       BIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) |           \
+       BIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) |              \
        BIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP))
 
 /* For idpf_splitq_base_tx_compl_desc */
diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h 
b/drivers/common/idpf/base/idpf_lan_vf_regs.h
index b5ff9b2cc9..4c5249129e 100644
--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h
@@ -94,14 +94,23 @@
  * b/w itrn registers of the same vector
  */
 #define VF_INT_ITR0(_ITR)              (0x00004C00 + ((_ITR) * 4))
-#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \
-                ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))
-/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and 
itrn_indx_spacing is 0x40 */
-#define VF_INT_ITRN(_INT, _ITR)        (0x00002800 + ((_INT) * 4) + ((_ITR) * 
0x40))
-/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and 
itrn_indx_spacing is 0x100 */
-#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 
0x100))
-/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and 
itrn_indx_spacing is 0x2000 */
-#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 
0x2000))
+#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing)  \
+       ((_reg_start) + ((_ITR) * (_itrn_indx_spacing)))
+/* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing
+ * is 0x40 and base register offset is 0x00002800
+ */
+#define VF_INT_ITRN(_INT, _ITR)                        \
+       (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))
+/* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing
+ * is 0x100 and base register offset is 0x00002C00
+ */
+#define VF_INT_ITRN_64(_INT, _ITR)     \
+       (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))
+/* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing
+ * is 0x2000 and base register offset is 0x00072000
+ */
+#define VF_INT_ITRN_2K(_INT, _ITR)     \
+       (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))
 #define VF_INT_ITRN_MAX_INDEX          2
 #define VF_INT_ITRN_INTERVAL_S         0
 #define VF_INT_ITRN_INTERVAL_M         IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S)
-- 
2.25.1

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