[PATCH v4 3/3] net/cpfl: refine Tx queue setup

[Simei Su]

This patch refines Tx single queue setup to align with Tx data path.

Signed-off-by: Simei Su <simei...@intel.com>
Acked-by: Wenjun Wu <wenjun1...@intel.com>
---
 drivers/net/cpfl/cpfl_rxtx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c
index 2ef6871a85..ab8bec4645 100644
--- a/drivers/net/cpfl/cpfl_rxtx.c
+++ b/drivers/net/cpfl/cpfl_rxtx.c
@@ -135,7 +135,7 @@ cpfl_dma_zone_reserve(struct rte_eth_dev *dev, uint16_t 
queue_idx,
                        ring_size = RTE_ALIGN(len * sizeof(struct 
idpf_flex_tx_sched_desc),
                                              CPFL_DMA_MEM_ALIGN);
                else
-                       ring_size = RTE_ALIGN(len * sizeof(struct 
idpf_flex_tx_desc),
+                       ring_size = RTE_ALIGN(len * sizeof(struct 
idpf_base_tx_desc),
                                              CPFL_DMA_MEM_ALIGN);
                memcpy(ring_name, "cpfl Tx ring", sizeof("cpfl Tx ring"));
                break;
-- 
2.25.1