This patch adds support to match opcode and dst_qp fields in
infiniband BTH. Currently, only the RoCEv2 packet is supported,
the input BTH match item is defaulted to match one RoCEv2 packet.
Signed-off-by: Dong Zhou <dongz...@nvidia.com>
Acked-by: Ori Kam <or...@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 5 +-
drivers/net/mlx5/mlx5_flow.h | 6 ++
drivers/net/mlx5/mlx5_flow_dv.c | 102 ++++++++++++++++++++++++++++++++
3 files changed, 111 insertions(+), 2 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index ed3d5efbb7..8f55fd59b3 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -932,7 +932,7 @@ struct mlx5_ifc_fte_match_set_misc_bits {
u8 gre_key_h[0x18];
u8 gre_key_l[0x8];
u8 vxlan_vni[0x18];
- u8 reserved_at_b8[0x8];
+ u8 bth_opcode[0x8];
u8 geneve_vni[0x18];
u8 lag_rx_port_affinity[0x4];
u8 reserved_at_e8[0x2];
@@ -945,7 +945,8 @@ struct mlx5_ifc_fte_match_set_misc_bits {
u8 reserved_at_120[0xa];
u8 geneve_opt_len[0x6];
u8 geneve_protocol_type[0x10];
- u8 reserved_at_140[0x20];
+ u8 reserved_at_140[0x8];
+ u8 bth_dst_qp[0x18];
u8 inner_esp_spi[0x20];
u8 outer_esp_spi[0x20];
u8 reserved_at_1a0[0x60];
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 1d116ea0f6..c1d6a71708 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -227,6 +227,9 @@ enum mlx5_feature_name {
/* Aggregated affinity item */
#define MLX5_FLOW_ITEM_AGGR_AFFINITY (UINT64_C(1) << 49)
+/* IB BTH ITEM. */
+#define MLX5_FLOW_ITEM_IB_BTH (1ull << 51)
+
/* Outer Masks. */
#define MLX5_FLOW_LAYER_OUTER_L3 \
(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
@@ -364,6 +367,9 @@ enum mlx5_feature_name {
#define MLX5_UDP_PORT_VXLAN 4789
#define MLX5_UDP_PORT_VXLAN_GPE 4790
+/* UDP port numbers for RoCEv2. */
+#define MLX5_UDP_PORT_ROCEv2 4791
+
/* UDP port numbers for GENEVE. */
#define MLX5_UDP_PORT_GENEVE 6081
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index d14661298c..a3b72dbb5f 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7193,6 +7193,65 @@ flow_dv_validate_item_flex(struct rte_eth_dev *dev,
return 0;
}
+/**
+ * Validate IB BTH item.
+ *
+ * @param[in] dev
+ * Pointer to the rte_eth_dev structure.
+ * @param[in] udp_dport
+ * UDP destination port
+ * @param[in] item
+ * Item specification.
+ * @param root
+ * Whether action is on root table.
+ * @param[out] error
+ * Pointer to the error structure.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+static int
+mlx5_flow_validate_item_ib_bth(struct rte_eth_dev *dev,
+ uint16_t udp_dport,
+ const struct rte_flow_item *item,
+ bool root,
+ struct rte_flow_error *error)
+{
+ const struct rte_flow_item_ib_bth *mask = item->mask;
+ struct mlx5_priv *priv = dev->data->dev_private;
+ const struct rte_flow_item_ib_bth *valid_mask;
+ int ret;
+
+ valid_mask = &rte_flow_item_ib_bth_mask;
+ if (udp_dport && udp_dport != MLX5_UDP_PORT_ROCEv2)
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "protocol filtering not compatible"
+ " with UDP layer");
+ if (mask && (mask->hdr.se || mask->hdr.m || mask->hdr.padcnt ||
+ mask->hdr.tver || mask->hdr.pkey || mask->hdr.f || mask->hdr.b
||
+ mask->hdr.rsvd0 || mask->hdr.a || mask->hdr.rsvd1 ||
+ mask->hdr.psn[0] || mask->hdr.psn[1] || mask->hdr.psn[2]))
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM, item,
+ "only opcode and dst_qp are
supported");
+ if (root || priv->sh->steering_format_version ==
+ MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5)
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM,
+ item,
+ "IB BTH item is not supported");
+ if (!mask)
+ mask = &rte_flow_item_ib_bth_mask;
+ ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
+ (const uint8_t *)valid_mask,
+ sizeof(struct rte_flow_item_ib_bth),
+ MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
+ if (ret < 0)
+ return ret;
+ return 0;
+}
+
/**
* Internal validation function. For validating both actions and items.
*
@@ -7700,6 +7759,14 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct
rte_flow_attr *attr,
return ret;
last_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;
break;
+ case RTE_FLOW_ITEM_TYPE_IB_BTH:
+ ret = mlx5_flow_validate_item_ib_bth(dev, udp_dport,
+ items, is_root,
error);
+ if (ret < 0)
+ return ret;
+
+ last_item = MLX5_FLOW_ITEM_IB_BTH;
+ break;
default:
return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM,
@@ -10971,6 +11038,37 @@ flow_dv_translate_item_aggr_affinity(void *key,
affinity_v->affinity & affinity_m->affinity);
}
+static void
+flow_dv_translate_item_ib_bth(void *key,
+ const struct rte_flow_item *item,
+ int inner, uint32_t key_type)
+{
+ const struct rte_flow_item_ib_bth *bth_m;
+ const struct rte_flow_item_ib_bth *bth_v;
+ void *headers_v, *misc_v;
+ uint16_t udp_dport;
+ char *qpn_v;
+ int i, size;
+
+ headers_v = inner ? MLX5_ADDR_OF(fte_match_param, key, inner_headers) :
+ MLX5_ADDR_OF(fte_match_param, key, outer_headers);
+ if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
+ udp_dport = key_type & MLX5_SET_MATCHER_M ?
+ 0xFFFF : MLX5_UDP_PORT_ROCEv2;
+ MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
udp_dport);
+ }
+ if (MLX5_ITEM_VALID(item, key_type))
+ return;
+ MLX5_ITEM_UPDATE(item, key_type, bth_v, bth_m,
&rte_flow_item_ib_bth_mask);
+ misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+ MLX5_SET(fte_match_set_misc, misc_v, bth_opcode,
+ bth_v->hdr.opcode & bth_m->hdr.opcode);
+ qpn_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, bth_dst_qp);
+ size = sizeof(bth_m->hdr.dst_qp);
+ for (i = 0; i < size; ++i)
+ qpn_v[i] = bth_m->hdr.dst_qp[i] & bth_v->hdr.dst_qp[i];
+}
+
static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
#define HEADER_IS_ZERO(match_criteria, headers)
\
@@ -13772,6 +13870,10 @@ flow_dv_translate_items(struct rte_eth_dev *dev,
flow_dv_translate_item_aggr_affinity(key, items, key_type);
last_item = MLX5_FLOW_ITEM_AGGR_AFFINITY;
break;
+ case RTE_FLOW_ITEM_TYPE_IB_BTH:
+ flow_dv_translate_item_ib_bth(key, items, tunnel, key_type);
+ last_item = MLX5_FLOW_ITEM_IB_BTH;
+ break;
default:
break;
}
--
2.27.0
