> From: Mattias Rönnblom [mailto:mattias.ronnb...@ericsson.com]
> Sent: Tuesday, 18 April 2023 14.31
>
> On 2023-04-18 12:45, Sivaprasad Tummala wrote:
> > fixed the padding required to align to cacheline size.
> >
>
> What's the point in having this structure cache-line aligned? False
> sharing is a non-issue, since this is more or less a read only struct.
>
> This is not so much a comment on your patch, but the __rte_cache_aligned
> attribute.
When the structure is cache aligned, an individual entry in the array does not
unnecessarily cross a cache line border. With 16 pointers and aligned, it uses
exactly two cache lines. If unaligned, it may span three cache lines.
>
> > Fixes: 54f17843a887 ("eventdev: add port maintenance API")
> > Cc: mattias.ronnb...@ericsson.com
> >
> > Signed-off-by: Sivaprasad Tummala <sivaprasad.tumm...@amd.com>
> > ---
> > lib/eventdev/rte_eventdev_core.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/lib/eventdev/rte_eventdev_core.h
> b/lib/eventdev/rte_eventdev_core.h
> > index c328bdbc82..c27a52ccc0 100644
> > --- a/lib/eventdev/rte_eventdev_core.h
> > +++ b/lib/eventdev/rte_eventdev_core.h
> > @@ -65,7 +65,7 @@ struct rte_event_fp_ops {
> > /**< PMD Tx adapter enqueue same destination function. */
> > event_crypto_adapter_enqueue_t ca_enqueue;
> > /**< PMD Crypto adapter enqueue function. */
> > - uintptr_t reserved[6];
> > + uintptr_t reserved[5];
> > } __rte_cache_aligned;
> >
> > extern struct rte_event_fp_ops rte_event_fp_ops[RTE_EVENT_MAX_DEVS];
