This patch adds the required functionality in the Octeon endpoint
driver to support the following CNX10K series endpoint devices.
- CN10KA
- CN10KB
- CNF10KA
- CNF10KB
Signed-off-by: Sathesh Edara <sed...@marvell.com>
---
drivers/net/octeon_ep/cnxk_ep_vf.h | 5 ++++-
drivers/net/octeon_ep/otx_ep_ethdev.c | 21 +++++++++++++++++----
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.h
b/drivers/net/octeon_ep/cnxk_ep_vf.h
index 7162461dd9..aaa5774552 100644
--- a/drivers/net/octeon_ep/cnxk_ep_vf.h
+++ b/drivers/net/octeon_ep/cnxk_ep_vf.h
@@ -134,7 +134,10 @@
#define CNXK_EP_R_OUT_CTL_ROR_P (1ULL << 24)
#define CNXK_EP_R_OUT_CTL_IMODE (1ULL << 23)
-#define PCI_DEVID_CNXK_EP_NET_VF 0xB903
+#define PCI_DEVID_CN10KA_EP_NET_VF 0xB903
+#define PCI_DEVID_CNF10KA_EP_NET_VF 0xBA03
+#define PCI_DEVID_CNF10KB_EP_NET_VF 0xBC03
+#define PCI_DEVID_CN10KB_EP_NET_VF 0xBD03
int
cnxk_ep_vf_setup_device(struct otx_ep_device *sdpvf);
diff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c
b/drivers/net/octeon_ep/otx_ep_ethdev.c
index 24f62c3e49..b23d52ff84 100644
--- a/drivers/net/octeon_ep/otx_ep_ethdev.c
+++ b/drivers/net/octeon_ep/otx_ep_ethdev.c
@@ -111,7 +111,10 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
ret = otx2_ep_vf_setup_device(otx_epvf);
otx_epvf->fn_list.disable_io_queues(otx_epvf);
break;
- case PCI_DEVID_CNXK_EP_NET_VF:
+ case PCI_DEVID_CN10KA_EP_NET_VF:
+ case PCI_DEVID_CN10KB_EP_NET_VF:
+ case PCI_DEVID_CNF10KA_EP_NET_VF:
+ case PCI_DEVID_CNF10KB_EP_NET_VF:
otx_epvf->chip_id = dev_id;
ret = cnxk_ep_vf_setup_device(otx_epvf);
otx_epvf->fn_list.disable_io_queues(otx_epvf);
@@ -150,7 +153,10 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)
otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF)
otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;
- else if (otx_epvf->chip_id == PCI_DEVID_CNXK_EP_NET_VF)
+ else if (otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||
+ otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF ||
+ otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF ||
+ otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF)
otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;
ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);
otx_epvf->max_rx_queues = ethdev_queues;
@@ -501,7 +507,11 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF ||
otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF ||
- otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF)
+ otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF ||
+ otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF ||
+ otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF ||
+ otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF ||
+ otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF)
otx_epvf->pkind = SDP_OTX2_PKIND_FS0;
else
otx_epvf->pkind = SDP_PKIND;
@@ -533,7 +543,10 @@ static const struct rte_pci_id pci_id_otx_ep_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95N_EP_NET_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95O_EP_NET_VF) },
- { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_EP_NET_VF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KA_EP_NET_VF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_EP_NET_VF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF10KA_EP_NET_VF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF10KB_EP_NET_VF) },
{ .vendor_id = 0, /* sentinel */ }
};
--
2.31.1
