On Tue, Apr 04, 2023 at 01:07:21PM -0700, Tyler Retzlaff wrote:
> Inline assembly is not supported for msvc x64 instead use
> _mm_{s,l,m}fence() intrinsics.
>
> Signed-off-by: Tyler Retzlaff <roret...@linux.microsoft.com>
> ---
> lib/eal/include/generic/rte_atomic.h | 4 ++++
> lib/eal/x86/include/rte_atomic.h | 10 +++++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/lib/eal/include/generic/rte_atomic.h
> b/lib/eal/include/generic/rte_atomic.h
> index 234b268..e973184 100644
> --- a/lib/eal/include/generic/rte_atomic.h
> +++ b/lib/eal/include/generic/rte_atomic.h
> @@ -116,9 +116,13 @@
> * Guarantees that operation reordering does not occur at compile time
> * for operations directly before and after the barrier.
> */
> +#ifndef RTE_TOOLCHAIN_MSVC
> #define rte_compiler_barrier() do { \
> asm volatile ("" : : : "memory"); \
> } while(0)
> +#else
> +#define rte_compiler_barrier() _ReadWriteBarrier()
> +#endif
>
> /**
> * Synchronization fence between threads based on the specified memory order.
> diff --git a/lib/eal/x86/include/rte_atomic.h
> b/lib/eal/x86/include/rte_atomic.h
> index f2ee1a9..7ae3a41 100644
> --- a/lib/eal/x86/include/rte_atomic.h
> +++ b/lib/eal/x86/include/rte_atomic.h
> @@ -27,9 +27,13 @@
>
> #define rte_rmb() _mm_lfence()
>
> +#ifndef RTE_TOOLCHAIN_MSVC
> #define rte_smp_wmb() rte_compiler_barrier()
> -
> #define rte_smp_rmb() rte_compiler_barrier()
> +#else
> +#define rte_smp_wmb() _mm_sfence()
> +#define rte_smp_rmb() _mm_lfence()
> +#endif
>
I think this change can be dropped from the diff. "rte_compiler_barrier()"
is valid in MSVC because you defined it above.
> /*
> * From Intel Software Development Manual; Vol 3;
> @@ -66,11 +70,15 @@
> static __rte_always_inline void
> rte_smp_mb(void)
> {
> +#ifndef RTE_TOOLCHAIN_MSVC
> #ifdef RTE_ARCH_I686
> asm volatile("lock addl $0, -128(%%esp); " ::: "memory");
> #else
> asm volatile("lock addl $0, -128(%%rsp); " ::: "memory");
> #endif
> +#else
> + _mm_mfence();
> +#endif
> }
>
> #define rte_io_mb() rte_mb()
> --
> 1.8.3.1
>
