Add capabilities check for LZ4 decompression algorithm.
Signed-off-by: Michael Baum <michae...@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++
drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++
drivers/common/mlx5/mlx5_prm.h | 16 ++++++++++++++--
3 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
b/drivers/common/mlx5/mlx5_devx_cmds.c
index dfec4dcf1b..f30daa19c7 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -989,6 +989,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
log_compress_mmo_size);
attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
log_decompress_mmo_size);
+ attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr,
+ decompress_lz4_data_only_v2);
+ attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
+ decompress_lz4_no_checksum_v2);
+ attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr,
+ decompress_lz4_checksum_v2);
attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
mini_cqe_resp_flow_tag);
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h
b/drivers/common/mlx5/mlx5_devx_cmds.h
index edb387e272..a82af9426d 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -267,6 +267,9 @@ struct mlx5_hca_attr {
uint32_t log_max_mmo_dma:5;
uint32_t log_max_mmo_compress:5;
uint32_t log_max_mmo_decompress:5;
+ uint32_t decomp_lz4_data_only_en:1;
+ uint32_t decomp_lz4_no_checksum_en:1;
+ uint32_t decomp_lz4_checksum_en:1;
uint32_t umr_modify_entity_size_disabled:1;
uint32_t umr_indirect_mkey_disabled:1;
uint32_t log_min_stride_wqe_sz:5;
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 377cbfab87..f89af8b96b 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -578,9 +578,19 @@ struct mlx5_rdma_write_wqe {
#define MLX5_OPC_MOD_MMO_DECOMP 0x3u
#define MLX5_OPC_MOD_MMO_DMA 0x1u
+#define WQE_GGA_DECOMP_DEFLATE 0x0u
+#define WQE_GGA_DECOMP_LZ4 0x2u
+
+#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITHOUT_CHECKSUM 0x1u
+#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITH_CHECKSUM 0x2u
+
#define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
#define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
#define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
+#define WQE_GGA_DECOMP_PARAMS_OFFSET 20u
+#define WQE_GGA_DECOMP_TYPE_OFFSET 8u
+#define WQE_GGA_DECOMP_BLOCK_INDEPENDENT_OFFSET 22u
+
#define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
#define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
#define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
@@ -599,7 +609,7 @@ struct mlx5_gga_wqe {
uint32_t opcode;
uint32_t sq_ds;
uint32_t flags;
- uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */
+ uint32_t gga_ctrl1;
uint32_t gga_ctrl2;
uint32_t opaque_lkey;
uint64_t opaque_vaddr;
@@ -1434,7 +1444,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 log_dma_mmo_size[0x5];
u8 reserved_at_70[0x3];
u8 log_compress_mmo_size[0x5];
- u8 reserved_at_78[0x3];
+ u8 decompress_lz4_data_only_v2[0x1];
+ u8 decompress_lz4_no_checksum_v2[0x1];
+ u8 decompress_lz4_checksum_v2[0x1];
u8 log_decompress_mmo_size[0x5];
u8 log_max_srq_sz[0x8];
u8 log_max_qp_sz[0x8];
--
2.25.1
