The generate WQE command is used as an interface to writing GTA
WQEs with fields that are not supported in current HW, for example
extended match definer.
Signed-off-by: Alex Vesker <va...@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 27 +++++++++++++++++-
drivers/net/mlx5/hws/mlx5dr_cmd.c | 47 +++++++++++++++++++++++++++++++
drivers/net/mlx5/hws/mlx5dr_cmd.h | 13 +++++++++
3 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 9294f65e24..d4d8ddcd2a 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1141,6 +1141,7 @@ enum {
MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16,
+ MLX5_CMD_OP_GENERATE_WQE = 0xb17,
};
enum {
@@ -2159,7 +2160,8 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {
u8 format_select_dw_gtpu_dw_1[0x8];
u8 format_select_dw_gtpu_dw_2[0x8];
u8 format_select_dw_gtpu_first_ext_dw_0[0x8];
- u8 reserved_at_2a0[0x560];
+ u8 generate_wqe_type[0x20];
+ u8 reserved_at_2c0[0x540];
};
struct mlx5_ifc_esw_cap_bits {
@@ -3529,6 +3531,29 @@ struct mlx5_ifc_create_alias_obj_in_bits {
struct mlx5_ifc_alias_context_bits alias_ctx;
};
+struct mlx5_ifc_generate_wqe_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mode[0x10];
+ u8 reserved_at_40[0x40];
+ u8 reserved_at_80[0x8];
+ u8 pdn[0x18];
+ u8 reserved_at_a0[0x160];
+ u8 wqe_ctrl[0x80];
+ u8 wqe_gta_ctrl[0x180];
+ u8 wqe_gta_data_0[0x200];
+ u8 wqe_gta_data_1[0x200];
+};
+
+struct mlx5_ifc_generate_wqe_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x1c0];
+ u8 cqe_data[0x200];
+};
+
enum {
MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c
b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 32378673cf..c648eacd03 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -795,6 +795,53 @@ mlx5dr_cmd_alias_obj_create(struct ibv_context *ctx,
return devx_obj;
}
+int mlx5dr_cmd_generate_wqe(struct ibv_context *ctx,
+ struct mlx5dr_cmd_generate_wqe_attr *attr,
+ struct mlx5_cqe64 *ret_cqe)
+{
+ uint32_t out[MLX5_ST_SZ_DW(generate_wqe_out)] = {0};
+ uint32_t in[MLX5_ST_SZ_DW(generate_wqe_in)] = {0};
+ uint8_t status;
+ void *ptr;
+ int ret;
+
+ MLX5_SET(generate_wqe_in, in, opcode, MLX5_CMD_OP_GENERATE_WQE);
+ MLX5_SET(generate_wqe_in, in, pdn, attr->pdn);
+
+ ptr = MLX5_ADDR_OF(generate_wqe_in, in, wqe_ctrl);
+ memcpy(ptr, attr->wqe_ctrl, MLX5_FLD_SZ_BYTES(generate_wqe_in,
wqe_ctrl));
+
+ ptr = MLX5_ADDR_OF(generate_wqe_in, in, wqe_gta_ctrl);
+ memcpy(ptr, attr->gta_ctrl, MLX5_FLD_SZ_BYTES(generate_wqe_in,
wqe_gta_ctrl));
+
+ ptr = MLX5_ADDR_OF(generate_wqe_in, in, wqe_gta_data_0);
+ memcpy(ptr, attr->gta_data_0, MLX5_FLD_SZ_BYTES(generate_wqe_in,
wqe_gta_data_0));
+
+ if (attr->gta_data_1) {
+ ptr = MLX5_ADDR_OF(generate_wqe_in, in, wqe_gta_data_1);
+ memcpy(ptr, attr->gta_data_1,
MLX5_FLD_SZ_BYTES(generate_wqe_in, wqe_gta_data_1));
+ }
+
+ ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
sizeof(out));
+ if (ret) {
+ DR_LOG(ERR, "Failed to write GTA WQE using FW");
+ rte_errno = errno;
+ return rte_errno;
+ }
+
+ status = MLX5_GET(generate_wqe_out, out, status);
+ if (status) {
+ DR_LOG(ERR, "Invalid FW CQE status %d", status);
+ rte_errno = EINVAL;
+ return rte_errno;
+ }
+
+ ptr = MLX5_ADDR_OF(generate_wqe_out, out, cqe_data);
+ memcpy(ret_cqe, ptr, sizeof(*ret_cqe));
+
+ return 0;
+}
+
int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
struct mlx5dr_cmd_query_caps *caps)
{
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h
b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index 468557ba16..3689d09897 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -153,6 +153,14 @@ struct mlx5dr_cmd_query_vport_caps {
uint32_t metadata_c_mask;
};
+struct mlx5dr_cmd_generate_wqe_attr {
+ uint8_t *wqe_ctrl;
+ uint8_t *gta_ctrl;
+ uint8_t *gta_data_0;
+ uint8_t *gta_data_1;
+ uint32_t pdn;
+};
+
struct mlx5dr_cmd_query_caps {
uint32_t wire_regc;
uint32_t wire_regc_mask;
@@ -212,6 +220,11 @@ int
mlx5dr_cmd_stc_modify(struct mlx5dr_devx_obj *devx_obj,
struct mlx5dr_cmd_stc_modify_attr *stc_attr);
+int
+mlx5dr_cmd_generate_wqe(struct ibv_context *ctx,
+ struct mlx5dr_cmd_generate_wqe_attr *attr,
+ struct mlx5_cqe64 *ret_cqe);
+
struct mlx5dr_devx_obj *
mlx5dr_cmd_ste_create(struct ibv_context *ctx,
struct mlx5dr_cmd_ste_create_attr *ste_attr);
--
2.18.1
