From: Satheesh Paul <psathe...@marvell.com>
When installing flow rule for second pass packets, set the
LA LTYPE to LA_CPT_HDR.
Fixes: 4968b362b63 ("common/cnxk: support CPT second pass flow rules")
Cc: sta...@dpdk.org
Signed-off-by: Satheesh Paul <psathe...@marvell.com>
Reviewed-by: Kiran Kumar K <kirankum...@marvell.com>
---
drivers/common/cnxk/roc_npc_mcam.c | 24 +++++++++++++++++-------
drivers/common/cnxk/roc_npc_mcam_dump.c | 6 ++++--
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/common/cnxk/roc_npc_mcam.c
b/drivers/common/cnxk/roc_npc_mcam.c
index 312424d1c2..06f3212e8d 100644
--- a/drivers/common/cnxk/roc_npc_mcam.c
+++ b/drivers/common/cnxk/roc_npc_mcam.c
@@ -668,22 +668,32 @@ npc_mcam_alloc_and_write(struct npc *npc, struct
roc_npc_flow *flow,
npc_mcam_set_channel(flow, req, npc->channel,
(BIT_ULL(12) - 1),
pst->is_second_pass_rule);
}
- /* Always match both 1st pass and 2nd pass ltypes for all rules
*/
- if (!pst->is_second_pass_rule && pst->has_eth_type) {
+ /*
+ * For second pass rule, set LA LTYPE to CPT_HDR.
+ * For all other rules, set LA LTYPE to match both 1st pass and
2nd pass ltypes.
+ */
+ if (pst->is_second_pass_rule || (!pst->is_second_pass_rule &&
pst->has_eth_type)) {
la_offset =
__builtin_popcount(npc->keyx_supp_nmask[flow->nix_intf] &
((1ULL << 9 /* LA offset
*/) - 1));
la_offset *= 4;
mask = ~((0xfULL << la_offset));
- /* Mask ltype ETHER (0x2) and CPT_HDR (0xa) */
req->entry_data.kw[0] &= mask;
req->entry_data.kw_mask[0] &= mask;
- req->entry_data.kw[0] |= (0x2ULL << la_offset);
- req->entry_data.kw_mask[0] |= (0x7ULL << la_offset);
flow->mcam_data[0] &= mask;
flow->mcam_mask[0] &= mask;
- flow->mcam_data[0] |= (0x2ULL << la_offset);
- flow->mcam_mask[0] |= (0x7ULL << la_offset);
+ if (pst->is_second_pass_rule) {
+ req->entry_data.kw[0] |=
((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset;
+ req->entry_data.kw_mask[0] |= (0xFULL <<
la_offset);
+ flow->mcam_data[0] |=
((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset;
+ flow->mcam_mask[0] |= (0xFULL << la_offset);
+ } else {
+ /* Mask ltype ETHER (0x2) and CPT_HDR (0xa) */
+ req->entry_data.kw[0] |= (0x2ULL << la_offset);
+ req->entry_data.kw_mask[0] |= (0x7ULL <<
la_offset);
+ flow->mcam_data[0] |= (0x2ULL << la_offset);
+ flow->mcam_mask[0] |= (0x7ULL << la_offset);
+ }
}
} else {
uint16_t pf_func = (flow->npc_action >> 4) & 0xffff;
diff --git a/drivers/common/cnxk/roc_npc_mcam_dump.c
b/drivers/common/cnxk/roc_npc_mcam_dump.c
index 2aaa2ac671..40909b45e6 100644
--- a/drivers/common/cnxk/roc_npc_mcam_dump.c
+++ b/drivers/common/cnxk/roc_npc_mcam_dump.c
@@ -69,8 +69,10 @@ static const char *const ltype_str[NPC_MAX_LID][NPC_MAX_LT]
= {
[NPC_LID_LA][NPC_LT_LA_IH_NIX_ETHER] = "LA_IH_NIX_ETHER",
[NPC_LID_LA][NPC_LT_LA_HIGIG2_ETHER] = "LA_HIGIG2_ETHER",
[NPC_LID_LA][NPC_LT_LA_IH_NIX_HIGIG2_ETHER] = "LA_IH_NIX_HIGIG2_ETHER",
- [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] =
- "NPC_LT_LA_CUSTOM_PRE_L2_ETHER",
+ [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_90B_ETHER] = "LA_CUSTOM_L2_90B_ETHER",
+ [NPC_LID_LA][NPC_LT_LA_CPT_HDR] = "LA_CPT_HDR",
+ [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_24B_ETHER] = "LA_CUSTOM_L2_24B_ETHER",
+ [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] =
"NPC_LT_LA_CUSTOM_PRE_L2_ETHER",
[NPC_LID_LB][0] = "NONE",
[NPC_LID_LB][NPC_LT_LB_CTAG] = "LB_CTAG",
[NPC_LID_LB][NPC_LT_LB_STAG_QINQ] = "LB_STAG_QINQ",
--
2.35.3
