Bluefield-3 and above devices use aes_xts_multi_block_be_tweak
bit to indicate AES-XTS capability. The devices below use
aes_xts_single_block_le_tweak bit.
This commit adds the AES-XTS attribute set while one of the
bits is set to make the attribute compatible with all the
devices.
Signed-off-by: Suanming Mou <suanmi...@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 4 +++-
drivers/common/mlx5/mlx5_prm.h | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
b/drivers/common/mlx5/mlx5_devx_cmds.c
index 59cebb530f..e3a4927d0f 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1013,7 +1013,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr,
flow_access_aso_opc_mod);
if (attr->crypto) {
- attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
+ attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) ||
+ MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) ||
+ MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak);
hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
MLX5_GET_HCA_CAP_OP_MOD_CRYPTO |
MLX5_HCA_CAP_OPMOD_GET_CUR);
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 2b5c43ee6e..6ec5185a7c 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1679,7 +1679,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 log_min_hairpin_wq_data_sz[0x5];
u8 reserved_at_3e8[0x3];
u8 log_max_vlan_list[0x5];
- u8 reserved_at_3f0[0x3];
+ u8 reserved_at_3f0[0x1];
+ u8 aes_xts_single_block_le_tweak[1];
+ u8 aes_xts_multi_block_be_tweak[1];
u8 log_max_current_mc_list[0x5];
u8 reserved_at_3f8[0x3];
u8 log_max_current_uc_list[0x5];
--
2.25.1
