Hi Thomas, > -----Original Message----- > From: Thomas Monjalon <tho...@monjalon.net> > Sent: Tuesday, November 22, 2022 7:01 AM > To: Chautru, Nicolas <nicolas.chau...@intel.com> > Cc: dev@dpdk.org; gak...@marvell.com; maxime.coque...@redhat.com; > Vargas, Hernan <hernan.var...@intel.com> > Subject: Re: [PATCH v2 2/2] doc: simplify the binding steps > > 15/11/2022 20:59, Nicolas Chautru: > > -The PCI virtual functions must be configured before working or > > getting assigned -to VMs/Containers. The configuration involves > > allocating the number of hardware > > +The device must be configured to work properly. > > +The configuration involves allocating the number of hardware > > queues, priorities, load balance, bandwidth and other settings > > necessary for the device to perform FEC functions. > > > > This configuration needs to be executed at least once after reboot or > > PCI FLR and can -be achieved by using the functions > > ``rte_acc10x_configure()``, > > +be achieved by either using ``pf_bb_config`` or the function > > +``rte_acc10x_configure()``, > > which sets up the parameters defined in the compatible ``acc100_conf`` > structure. > > +This is the method used in the bbdev-test test application. > > Clearly this patch is more than "simplifying binding steps". >
The intent has indeed to remove much of the binding steps to point to generic document, then minor updates to keep the flow readable and informative. Let me know what you are referring to specifically which caught your eyes. Some of the FPGA configuration steps were also simplifies to align with the other PMDs. We can rename if you prefer as doc: simplify the binding and configuration steps. Or split but unsure of the value. Up to you. Thanks Nic
