Update IPsec handling with reference from UCODE version
OCPT-04-IE-IPSEC-MC-30-01-28-00
Signed-off-by: Rahul Bhansali <rbhans...@marvell.com>
---
drivers/net/cnxk/cn10k_rx.h | 170 ++++++++++++++++++++----------------
1 file changed, 95 insertions(+), 75 deletions(-)
diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 4e22ceda02..ff01c2d8b3 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -42,17 +42,12 @@
(uint64_t *)(((uintptr_t)((uint64_t *)(b))[i]) - (o)) : \
(uint64_t *)(((uintptr_t)(b)) + CQE_SZ(i) - (o)))
-#define NIX_RX_SEC_UCC_CONST
\
- ((RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1) << 8 | \
- ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \
- << 24 | \
- ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1) \
- << 32 | \
- ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \
- << 40 | \
- ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \
- << 48 | \
- (RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1) << 56)
+#define NIX_RX_SEC_UCC_CONST
\
+ ((RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1) |
\
+ ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) <<
8 | \
+ ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1) <<
16 | \
+ ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) <<
32 | \
+ ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) <<
48)
#ifdef RTE_LIBRTE_MEMPOOL_DEBUG
static inline void
@@ -475,16 +470,23 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5,
const uint64_t sa_base,
inner->data_len = len;
*(uint64_t *)(&inner->rearm_data) = mbuf_init;
- inner->ol_flags = ((ucc == CPT_COMP_WARN) ?
+ inner->ol_flags = ((CPT_COMP_HWGOOD_MASK & (1U << ucc))
?
RTE_MBUF_F_RX_SEC_OFFLOAD :
(RTE_MBUF_F_RX_SEC_OFFLOAD |
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED));
ucc = hdr->w3.uc_ccode;
- inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?
- ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))
- & 0xFF) << 1 : 0;
- } else if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) {
+
+ if (ucc && ucc < 0xED) {
+ inner->ol_flags |=
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
+ } else {
+ ucc += 3; /* To make codes in 0xFx series
except 0 */
+ inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?
+ ((NIX_RX_SEC_UCC_CONST >>
((ucc & 0xF) << 3))
+ & 0xFF) << 1 :
RTE_MBUF_F_RX_IP_CKSUM_GOOD;
+ }
+ } else if ((!(hdr->w0.err_sum) ||
roc_ie_ot_ucc_is_success(hdr->w3.uc_ccode)) &&
+ !(hdr->w0.reas_sts)) {
/* Reassembly success */
inner = nix_sec_reassemble_frags(hdr, cq_w1, cq_w5,
mbuf_init);
@@ -541,15 +543,21 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5,
const uint64_t sa_base,
inner->data_len = len;
*(uint64_t *)(&inner->rearm_data) = mbuf_init;
- inner->ol_flags = ((ucc == CPT_COMP_WARN) ?
+ inner->ol_flags = ((CPT_COMP_HWGOOD_MASK & (1U << ucc)) ?
RTE_MBUF_F_RX_SEC_OFFLOAD :
(RTE_MBUF_F_RX_SEC_OFFLOAD |
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED));
ucc = hdr->w3.uc_ccode;
- inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?
- ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))
- & 0xFF) << 1 : 0;
+
+ if (ucc && ucc < 0xED) {
+ inner->ol_flags |= RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
+ } else {
+ ucc += 3; /* To make codes in 0xFx series except 0 */
+ inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?
+ ((NIX_RX_SEC_UCC_CONST >> ((ucc &
0xF) << 3))
+ & 0xFF) << 1 :
RTE_MBUF_F_RX_IP_CKSUM_GOOD;
+ }
/* Store meta in lmtline to free
* Assume all meta's from same aura.
@@ -596,7 +604,8 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5,
uintptr_t inb_sa,
RTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1);
if (flags & NIX_RX_REAS_F && hdr->w0.num_frags) {
- if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) {
+ if ((!(hdr->w0.err_sum) ||
roc_ie_ot_ucc_is_success(hdr->w3.uc_ccode)) &&
+ !(hdr->w0.reas_sts)) {
/* Reassembly success */
nix_sec_reassemble_frags(hdr, cq_w1, cq_w5, mbuf_init);
@@ -1317,6 +1326,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf
**mbufs, uint16_t pkts,
uintptr_t cpth1 = (uintptr_t)mbuf1 + d_off;
uintptr_t cpth2 = (uintptr_t)mbuf2 + d_off;
uintptr_t cpth3 = (uintptr_t)mbuf3 + d_off;
+ uint8_t code;
uint64x2_t inner0, inner1, inner2, inner3;
uint64x2_t wqe01, wqe23, sa01, sa23;
@@ -1352,42 +1362,46 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf
**mbufs, uint16_t pkts,
sa01 = vaddq_u64(sa01, vdupq_n_u64(sa_base));
sa23 = vaddq_u64(sa23, vdupq_n_u64(sa_base));
- const uint8x16_t tbl = {
- /* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST */
- 0,
- /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM */
- RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
- /* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN */
- 0,
- /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM */
- (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
- RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
- /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM */
- (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
- RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
- /* ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM */
- (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
- RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
- /* ROC_IE_OT_UCC_SUCCESS_PKT_UDP_ZEROCSUM */
- (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
- RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
- /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM */
- RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1,
- /* HW_CCODE -> RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED
*/
- 1, 0, 1, 1, 1, 1, 0, 1,
- };
-
- const int8x8_t err_off = {
- /* UCC of significance starts from 0xF0 */
- 0xF0,
- /* Move HW_CCODE from 0:6 -> 8:14 */
- -8,
- 0xF0,
- -8,
- 0xF0,
- -8,
- 0xF0,
- -8,
+ const uint8x16x2_t tbl = {{
+ {
+ /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM
*/
+ RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
+ /*
ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM */
+ (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
+ RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
+ /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM
*/
+ (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
+ RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
+ 1,
+ /*
ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM */
+ (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
+ RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
+ 1,
+ /*
ROC_IE_OT_UCC_SUCCESS_PKT_UDP_ZEROCSUM */
+ (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
+ RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
+ 3, 1, 3, 3, 3, 3, 1, 3, 1,
+ },
+ {
+ 1, 1, 1,
+ /*
ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM */
+ RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1,
+ /* Rest 0 to indicate
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ },
+ }};
+
+ const uint8x8_t err_off = {
+ /* UCC */
+ 0xED,
+ /* HW_CCODE 0:6 -> 7:D */
+ -7,
+ 0xED,
+ -7,
+ 0xED,
+ -7,
+ 0xED,
+ -7,
};
ucc = vdup_n_u8(0);
@@ -1395,8 +1409,13 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf
**mbufs, uint16_t pkts,
ucc = vset_lane_u16(*(uint16_t *)(cpth1 + 30), ucc, 1);
ucc = vset_lane_u16(*(uint16_t *)(cpth2 + 30), ucc, 2);
ucc = vset_lane_u16(*(uint16_t *)(cpth3 + 30), ucc, 3);
- ucc = vsub_s8(ucc, err_off);
- ucc = vqtbl1_u8(tbl, ucc);
+ ucc = vsub_u8(ucc, err_off);
+
+ /* Table lookup to get the corresponding flags, Out of
the range
+ * from this lookup will have value 0 and consider as
+ * RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED.
+ */
+ ucc = vqtbl2_u8(tbl, ucc);
RTE_BUILD_BUG_ON(NPC_LT_LC_IP != 2);
RTE_BUILD_BUG_ON(NPC_LT_LC_IP_OPT != 3);
@@ -1478,10 +1497,11 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf
**mbufs, uint16_t pkts,
nix_sec_meta_to_mbuf(cq0_w1, cq0_w5, sa, cpth0,
mbuf0, &f0, &ol_flags0,
flags, &rearm0);
- ol_flags0 |= ((uint64_t)vget_lane_u8(ucc, 0))
- << 1;
- ol_flags0 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |
- (uint64_t)vget_lane_u8(ucc, 1) << 19);
+ code = vget_lane_u8(ucc, 0);
+ ol_flags0 |= code ? (code > 1 ?
((uint64_t)code) << 1 : 0) :
+
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
+
+ ol_flags0 |= ((uint64_t)(vget_lane_u8(ucc, 1))
<< 18);
}
if (cq1_w1 & BIT(11)) {
@@ -1502,10 +1522,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf
**mbufs, uint16_t pkts,
nix_sec_meta_to_mbuf(cq1_w1, cq1_w5, sa, cpth1,
mbuf1, &f1, &ol_flags1,
flags, &rearm1);
- ol_flags1 |= ((uint64_t)vget_lane_u8(ucc, 2))
- << 1;
- ol_flags1 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |
- (uint64_t)vget_lane_u8(ucc, 3) << 19);
+ code = vget_lane_u8(ucc, 2);
+ ol_flags1 |= code ? (code > 1 ?
((uint64_t)code) << 1 : 0) :
+
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
+ ol_flags1 |= ((uint64_t)(vget_lane_u8(ucc, 3))
<< 18);
}
if (cq2_w1 & BIT(11)) {
@@ -1526,10 +1546,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf
**mbufs, uint16_t pkts,
nix_sec_meta_to_mbuf(cq2_w1, cq2_w5, sa, cpth2,
mbuf2, &f2, &ol_flags2,
flags, &rearm2);
- ol_flags2 |= ((uint64_t)vget_lane_u8(ucc, 4))
- << 1;
- ol_flags2 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |
- (uint64_t)vget_lane_u8(ucc, 5) << 19);
+ code = vget_lane_u8(ucc, 4);
+ ol_flags2 |= code ? (code > 1 ?
((uint64_t)code) << 1 : 0) :
+
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
+ ol_flags2 |= ((uint64_t)(vget_lane_u8(ucc, 5))
<< 18);
}
if (cq3_w1 & BIT(11)) {
@@ -1550,10 +1570,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf
**mbufs, uint16_t pkts,
nix_sec_meta_to_mbuf(cq3_w1, cq3_w5, sa, cpth3,
mbuf3, &f3, &ol_flags3,
flags, &rearm3);
- ol_flags3 |= ((uint64_t)vget_lane_u8(ucc, 6))
- << 1;
- ol_flags3 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |
- (uint64_t)vget_lane_u8(ucc, 7) << 19);
+ code = vget_lane_u8(ucc, 6);
+ ol_flags3 |= code ? (code > 1 ?
((uint64_t)code) << 1 : 0) :
+
RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;
+ ol_flags3 |= ((uint64_t)(vget_lane_u8(ucc, 7))
<< 18);
}
}
--
2.25.1
