On Mon, 2 Nov 2015 11:23:05 +0530
Jerin Jacob <jerin.jacob at caviumnetworks.com> wrote:
--snip--
> > +#ifndef _RTE_ATOMIC_ARM_H_
> > +#define _RTE_ATOMIC_ARM_H_
> > +
> > +#ifdef __cplusplus
> > +extern "C" {
> > +#endif
> > +
> > +#include "generic/rte_atomic.h"
> > +
> > +/**
> > + * General memory barrier.
> > + *
> > + * Guarantees that the LOAD and STORE operations generated before the
> > + * barrier occur before the LOAD and STORE operations generated after.
> > + */
> > +#define rte_mb() __sync_synchronize()
> > +
> > +/**
> > + * Write memory barrier.
> > + *
> > + * Guarantees that the STORE operations generated before the barrier
> > + * occur before the STORE operations generated after.
> > + */
> > +#define rte_wmb() do { asm volatile ("dmb st" : : : "memory"); } while
> > (0)
> > +
> > +/**
> > + * Read memory barrier.
> > + *
> > + * Guarantees that the LOAD operations generated before the barrier
> > + * occur before the LOAD operations generated after.
> > + */
> > +#define rte_rmb() __sync_synchronize()
> > +
>
> #define dmb(opt) asm volatile("dmb " #opt : : : "memory")
>
> static inline void rte_mb(void)
> {
> dmb(ish);
> }
>
> static inline void rte_wmb(void)
> {
> dmb(ishst);
> }
>
> static inline void rte_rmb(void)
> {
> dmb(ishld);
I cannot see this option in the doc for ARMv7
(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0588b/CIHGHHIE.html).
> }
>
> For armv8, it make sense to have above definition for rte_*mb().
If it is OK to restrict the barriers to the inner-domain then OK. Quite
frankly, I don't know.
> If doesn't make sense for armv7 then we need split this file
> rte_atomic_32/64.h
>
>
--
Jan Viktorin E-mail: Viktorin at RehiveTech.com
System Architect Web: www.RehiveTech.com
RehiveTech
Brno, Czech Republic
