On Fri, Oct 30, 2015 at 01:49:16PM +0000, David Hunt wrote:
> Signed-off-by: David Hunt <david.hunt at intel.com>
> ---
> .../common/include/arch/arm/rte_cycles.h | 4 ++
> .../common/include/arch/arm/rte_cycles_64.h | 77
> ++++++++++++++++++++++
> 2 files changed, 81 insertions(+)
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles.h
> b/lib/librte_eal/common/include/arch/arm/rte_cycles.h
> index b2372fa..a8009a0 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_cycles.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles.h
> @@ -33,6 +33,10 @@
> #ifndef _RTE_CYCLES_ARM_H_
> #define _RTE_CYCLES_ARM_H_
>
> +#ifdef RTE_ARCH_64
> +#include <rte_cycles_64.h>
> +#else
> #include <rte_cycles_32.h>
> +#endif
>
> #endif /* _RTE_CYCLES_ARM_H_ */
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> new file mode 100644
> index 0000000..148b9f4
> --- /dev/null
> +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h
> @@ -0,0 +1,77 @@
> +/*
> + * BSD LICENSE
> + *
> + * Copyright (C) IBM Corporation 2014.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + *
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in
> + * the documentation and/or other materials provided with the
> + * distribution.
> + * * Neither the name of IBM Corporation nor the names of its
> + * contributors may be used to endorse or promote products derived
> + * from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> +*/
> +
> +#ifndef _RTE_CYCLES_ARM64_H_
> +#define _RTE_CYCLES_ARM64_H_
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "generic/rte_cycles.h"
> +
> +/**
> + * Read the time base register.
> + *
> + * @return
> + * The time base for this lcore.
> + */
> +static inline uint64_t
> +rte_rdtsc(void)
> +{
> + uint64_t tsc;
> +
> + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (tsc));
> +
> +#ifdef RTE_TIMER_MULTIPLIER
> + return tsc * RTE_TIMER_MULTIPLIER;
> +#else
> + return tsc;
> +#endif
> +
> +}
> +
> +static inline uint64_t
> +rte_rdtsc_precise(void)
> +{
> + asm volatile("isb sy" :::);
IMO, it should be asm volatile("dmb ish" : : : "memory")
to represent the data memory barrier(rte_mb()).
> + return rte_rdtsc();
> +}
> +
> +static inline uint64_t
> +rte_get_tsc_cycles(void) { return rte_rdtsc(); }
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* _RTE_CYCLES_ARM64_H_ */
> --
> 1.9.1
>
