On 9/5/22 13:58, Junfeng Guo wrote:
Add support for timestamp offload.
Signed-off-by: Wenjing Qiao <wenjing.q...@intel.com>
Signed-off-by: Junfeng Guo <junfeng....@intel.com>
[snip]
+/* Helper function to convert a 32b nanoseconds timestamp to 64b. */
+static inline uint64_t
+idpf_tstamp_convert_32b_64b(struct iecm_hw *hw, struct idpf_adapter *ad,
+ uint32_t flag, uint32_t in_timestamp)
+{
+/* TODO: timestamp for ACC */
+#ifdef RTE_ARCH_ARM64
+ return 0;
+#endif /* RTE_ARCH_ARM64 */
+
+#ifdef RTE_ARCH_X86_64
+ const uint64_t mask = 0xFFFFFFFF;
+ uint32_t hi, lo, lo2, delta;
+ uint64_t ns;
+
+ if (flag) {
+ IECM_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ IECM_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |
+ PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ lo = IECM_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IECM_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ /*
+ * On typical system, the delta between lo and lo2 is ~1000ns,
+ * so 10000 seems a large-enough but not overly-big guard band.
+ */
+ if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
+ lo2 = IECM_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ else
+ lo2 = lo;
+
+ if (lo2 < lo) {
+ lo = IECM_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IECM_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ }
+
+ ad->time_hw = ((uint64_t)hi << 32) | lo;
+ }
+
+ delta = (in_timestamp - (uint32_t)(ad->time_hw & mask));
+ if (delta > (mask / 2)) {
+ delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);
+ ns = ad->time_hw - delta;
+ } else {
+ ns = ad->time_hw + delta;
+ }
+
+ return ns;
+#endif /* RTE_ARCH_X86_64 */
Conditional compilation is rather strange above.
Will it break build on some architectures?
Non-x86-64 and non-ARM64.
+}
+#endif /* _IDPF_RXTX_H_ */
