- Added SM3 hash algorithm.
Signed-off-by: Arek Kusztal <arkadiuszx.kusz...@intel.com>
---
doc/guides/cryptodevs/features/qat.ini | 1 +
doc/guides/rel_notes/release_22_11.rst | 3 +++
drivers/common/qat/qat_adf/icp_qat_hw.h | 2 +-
drivers/crypto/qat/qat_sym_session.c | 20 +++++++++++++++++++-
4 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/doc/guides/cryptodevs/features/qat.ini
b/doc/guides/cryptodevs/features/qat.ini
index edabc030d7..4508becc56 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -65,6 +65,7 @@ KASUMI F9 = Y
AES XCBC MAC = Y
ZUC EIA3 = Y
AES CMAC (128) = Y
+SM3 = Y
;
; Supported AEAD algorithms of the 'qat' crypto driver.
diff --git a/doc/guides/rel_notes/release_22_11.rst
b/doc/guides/rel_notes/release_22_11.rst
index c6638ded82..5fb79f741c 100644
--- a/doc/guides/rel_notes/release_22_11.rst
+++ b/doc/guides/rel_notes/release_22_11.rst
@@ -69,6 +69,9 @@ New Features
Added SM4 encryption algorithm to the QAT PMD.
Supported modes are ECB, CBC and CTR.
+ Added SM3 hash algorithm to the QAT PMD.
+
+
Removed Items
-------------
diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h
b/drivers/common/qat/qat_adf/icp_qat_hw.h
index b1e6a1fa15..f6875b5242 100644
--- a/drivers/common/qat/qat_adf/icp_qat_hw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_hw.h
@@ -46,7 +46,7 @@ enum icp_qat_hw_auth_algo {
ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
- ICP_QAT_HW_AUTH_RESERVED_1 = 15,
+ ICP_QAT_HW_AUTH_ALGO_SM3 = 15,
ICP_QAT_HW_AUTH_RESERVED_2 = 16,
ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
ICP_QAT_HW_AUTH_RESERVED_3 = 18,
diff --git a/drivers/crypto/qat/qat_sym_session.c
b/drivers/crypto/qat/qat_sym_session.c
index f4e0faa8e1..6996c3499b 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -687,6 +687,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
session->digest_length = auth_xform->digest_length;
switch (auth_xform->algo) {
+ case RTE_CRYPTO_AUTH_SM3:
+ session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SM3;
+ session->auth_mode = ICP_QAT_HW_AUTH_MODE2;
+ break;
case RTE_CRYPTO_AUTH_SHA1:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
session->auth_mode = ICP_QAT_HW_AUTH_MODE0;
@@ -1092,6 +1096,8 @@ static int qat_hash_get_block_size(enum
icp_qat_hw_auth_algo qat_hash_alg)
return ICP_QAT_HW_AES_BLK_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
return MD5_CBLOCK;
+ case ICP_QAT_HW_AUTH_ALGO_SM3:
+ return 64;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum block size in this case */
return SHA512_CBLOCK;
@@ -2035,7 +2041,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
|| cdesc->is_cnt_zero
)
hash->auth_counter.counter = 0;
- else {
+ else if (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE1) {
int block_size = qat_hash_get_block_size(cdesc->qat_hash_alg);
if (block_size < 0)
@@ -2048,7 +2054,19 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
/*
* cd_cur_ptr now points at the state1 information.
*/
+ uint8_t state1[] = {
+ 0x73, 0x80, 0x16, 0x6f, 0x49, 0x14, 0xb2, 0xb9,
+ 0x17, 0x24, 0x42, 0xd7, 0xda, 0x8a, 0x06, 0x00,
+ 0xa9, 0x6f, 0x30, 0xbc, 0x16, 0x31, 0x38, 0xaa,
+ 0xe3, 0x8d, 0xee, 0x4d, 0xb0, 0xfb, 0x0e, 0x4e
+ };
switch (cdesc->qat_hash_alg) {
+ case ICP_QAT_HW_AUTH_ALGO_SM3:
+ rte_memcpy(cdesc->cd_cur_ptr, state1,
+ sizeof(state1));
+ state1_size = 32;
+ state2_size = 32;
+ break;
case ICP_QAT_HW_AUTH_ALGO_SHA1:
if (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) {
/* Plain SHA-1 */
--
2.13.6
