Hi, > -----Original Message----- > From: Gregory Etelson <getel...@nvidia.com> > Sent: Monday, July 4, 2022 1:12 PM > To: dev@dpdk.org > Cc: Gregory Etelson <getel...@nvidia.com>; Matan Azrad > <ma...@nvidia.com>; Raslan Darawsheh <rasl...@nvidia.com>; Raja > Zidane <rzid...@nvidia.com>; sta...@dpdk.org; Slava Ovsiienko > <viachesl...@nvidia.com> > Subject: [PATCH v4] net/mlx5: reject negative integrity item configuration > > From: Raja Zidane <rzid...@nvidia.com> > > Negative integrity item refers to condition when the item value mask > is set, but value spec is cleared: > ... integrity value mask l4_ok value spec 0 ... > > RTE library defines integrity bits `l3_ok` and `l4_ok` as accumulators > for all hardware L3 and L4 integrity verifications respectfully. > Hardware `l3_ok` and `l4_ok` integrity bits refer to L3 and L4 > network headers only. > Integrity bits `l3_ok` and `l4_ok` are not compatible between RTE > library and hardware. > > PMD translations for RTE `l3_ok` are: > IPv4: `l3_ok` and `l3_csum_ok` > IPv6: `l3_ok` > RTE `l4_ok` is translated into PMD `l4_ok` and `l4_csum_ok` bits. > > Positive IPv4 `l3_ok` flow item configuration is translated into > a single matcher that AND corresponding hardware bits. > Negative IPv4 `l3_ok` is translated into 2 hardware conditions where > each condition probes a single integrity bit: > RTE::l3_ok is 0 => MLX5::l3_ok is 0 OR MLX5:l3_csum_ok is 0 > MLX5 hardware does not do OR condition in flow rule item. > Negative IPv4 `l3_ok` must be translated into 2 flow rules. > Similarly negative RTE `l4_ok` condition is also translated into 2 > hardware rules. > > Current PMD roadmap does not allow implicit flow rule split. > > TODO: extend RTE integrity bits definition to allow match on each > hardware integrity bit for accumulated integiry matches. > > Bugzilla ID: 948 > > cc: sta...@dpdk.org > > Proposed-off-by: Raja Zidane rzid...@nvidia.com > Signed-off-by: Gregory Etelson <getel...@nvidia.com> > Acked-by: Matan Azrad <ma...@nvidia.com> > Acked-by: Viacheslav Ovsiienko <viachesl...@nvidia.com>
Patch applied to next-net-mlx, Kindest regards, Raslan Darawsheh
