Current MLX5 PMD documentation stays that entire `ConnentX-6` family
supports flow integrity feature.
Flow integrity offload is supported starting from `ConnectX-6 DX`.
Cc: sta...@dpdk.org
Fixes: 79f8952783d0 ("net/mlx5: support integrity flow item")
Signed-off-by: Gregory Etelson <getel...@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viachesl...@nvidia.com>
---
doc/guides/nics/mlx5.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index f41703277e..978886ad88 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -458,7 +458,7 @@ Limitations
- Integrity:
- - Integrity offload is enabled for **ConnectX-6** family.
+ - Integrity offload is enabled starting from **ConnectX-6 DX**.
- Verification bits provided by the hardware are ``l3_ok``,
``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.
- ``level`` value 0 references outer headers.
- Multiple integrity items not supported in a single flow rule.
--
2.34.1
