HI Chenbo,
Thanks for your reply.
I will send out a new version to fix this.
> -----Original Message-----
> From: Xia, Chenbo <chenbo....@intel.com>
> Sent: Friday, May 13, 2022 10:58 AM
> To: Pei, Andy <andy....@intel.com>; dev@dpdk.org
> Cc: maxime.coque...@redhat.com; Cao, Gang <gang....@intel.com>; Liu,
> Changpeng <changpeng....@intel.com>
> Subject: RE: [PATCH v7 16/18] vdpa/ifc/base: access correct register for blk
> device
>
> > -----Original Message-----
> > From: Pei, Andy <andy....@intel.com>
> > Sent: Wednesday, April 27, 2022 4:30 PM
> > To: dev@dpdk.org
> > Cc: Xia, Chenbo <chenbo....@intel.com>; maxime.coque...@redhat.com;
> > Cao, Gang <gang....@intel.com>; Liu, Changpeng
> > <changpeng....@intel.com>
> > Subject: [PATCH v7 16/18] vdpa/ifc/base: access correct register for
> > blk device
> >
> > 1.last_avail_idx is lower 16 bit of the register.
> > 2.address of ring_state register is different between net and blk device.
>
> Not a good commit log. The commit log should illustrate more on what's the
> commit is doing.
>
> Thanks,
> Chenbo
>
> >
> > Signed-off-by: Andy Pei <andy....@intel.com>
> > ---
> > drivers/vdpa/ifc/base/ifcvf.c | 36
> > +++++++++++++++++++++++++++++-------
> > drivers/vdpa/ifc/base/ifcvf.h | 1 +
> > 2 files changed, 30 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/vdpa/ifc/base/ifcvf.c
> > b/drivers/vdpa/ifc/base/ifcvf.c index d10c1fd..4d5881a 100644
> > --- a/drivers/vdpa/ifc/base/ifcvf.c
> > +++ b/drivers/vdpa/ifc/base/ifcvf.c
> > @@ -218,10 +218,18 @@
> > &cfg->queue_used_hi);
> > IFCVF_WRITE_REG16(hw->vring[i].size, &cfg->queue_size);
> >
> > - *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET +
> > - (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4) =
> > - (u32)hw->vring[i].last_avail_idx |
> > - ((u32)hw->vring[i].last_used_idx << 16);
> > + if (hw->is_blk == IFCVF_BLK) {
> > + *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET +
> > + i * IFCVF_LM_CFG_SIZE) =
> > + (u32)hw->vring[i].last_avail_idx |
> > + ((u32)hw->vring[i].last_used_idx << 16);
> > + } else if (hw->is_blk == IFCVF_NET) {
> > + *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET +
> > + (i / 2) * IFCVF_LM_CFG_SIZE +
> > + (i % 2) * 4) =
> > + (u32)hw->vring[i].last_avail_idx |
> > + ((u32)hw->vring[i].last_used_idx << 16);
> > + }
> >
> > IFCVF_WRITE_REG16(i + 1, &cfg->queue_msix_vector);
> > if (IFCVF_READ_REG16(&cfg->queue_msix_vector) == @@ -
> 254,9 +262,23
> > @@
> > IFCVF_WRITE_REG16(i, &cfg->queue_select);
> > IFCVF_WRITE_REG16(0, &cfg->queue_enable);
> > IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg-
> > >queue_msix_vector);
> > - ring_state = *(u32 *)(hw->lm_cfg +
> IFCVF_LM_RING_STATE_OFFSET
> > +
> > - (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4);
> > - hw->vring[i].last_avail_idx = (u16)(ring_state >> 16);
> > +
> > + if (hw->is_blk) {
> > + ring_state = *(u32 *)(hw->lm_cfg +
> > + IFCVF_LM_RING_STATE_OFFSET +
> > + i * IFCVF_LM_CFG_SIZE);
> > + } else if (hw->is_blk == IFCVF_NET) {
> > + ring_state = *(u32 *)(hw->lm_cfg +
> > + IFCVF_LM_RING_STATE_OFFSET +
> > + (i / 2) * IFCVF_LM_CFG_SIZE +
> > + (i % 2) * 4);
> > + }
> > +
> > + if (hw->is_blk == IFCVF_BLK)
> > + hw->vring[i].last_avail_idx =
> > + (u16)(ring_state & IFCVF_16_BIT_MASK);
> > + else if (hw->is_blk == IFCVF_NET)
> > + hw->vring[i].last_avail_idx = (u16)(ring_state >> 16);
> > hw->vring[i].last_used_idx = (u16)(ring_state >> 16);
> > }
> > }
> > diff --git a/drivers/vdpa/ifc/base/ifcvf.h
> > b/drivers/vdpa/ifc/base/ifcvf.h index 8591ef1..ff11b12 100644
> > --- a/drivers/vdpa/ifc/base/ifcvf.h
> > +++ b/drivers/vdpa/ifc/base/ifcvf.h
> > @@ -65,6 +65,7 @@
> > #define IFCVF_MEDIATED_VRING 0x200000000000
> >
> > #define IFCVF_32_BIT_MASK 0xffffffff
> > +#define IFCVF_16_BIT_MASK 0xffff
> >
> > #ifndef VHOST_USER_PROTOCOL_F_CONFIG
> > #define VHOST_USER_PROTOCOL_F_CONFIG 9
> > --
> > 1.8.3.1
>
