> -----Original Message-----
> From: Bruce Richardson <bruce.richard...@intel.com>
> Sent: Thursday, May 5, 2022 8:09 PM
> To: Rahul Bhansali <rbhans...@marvell.com>
> Cc: dev@dpdk.org; Ruifeng Wang <ruifeng.w...@arm.com>; Jan Viktorin
> <vikto...@rehivetech.com>; Jerin Jacob Kollanukkaran <jer...@marvell.com>
> Subject: [EXT] Re: [PATCH 1/2] config/arm: add SVE control flag
>
> External Email
>
> ----------------------------------------------------------------------
> On Thu, May 05, 2022 at 07:57:43PM +0530, Rahul Bhansali wrote:
> > This add the control flag for SVE to enable or disable
> > RTE_HAS_SVE_ACLE macro in the build.
> >
> > Signed-off-by: Rahul Bhansali <rbhans...@marvell.com>
> > ---
> > config/arm/meson.build | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > 8aead74086..dafb342cc6 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args)
> != '' or
> > compile_time_cpuflags += ['RTE_CPUFLAG_NEON'] endif
> >
> > -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> > +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
> > + soc_config.get('sve', true))
>
> Please double-indent this so that it does not line up with the following
> lines of
> the block.
>
Ack, will send v2 with this double-indent change.
> > compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
> > if (cc.check_header('arm_sve.h'))
> > dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
> > --
> > 2.25.1
> >
