[RFC 03/15] common/mlx5: add DevX API to move QP to reset state

[Li Zhang]

From: Yajun Wu <yaj...@nvidia.com>

Support set QP to RESET state.

Signed-off-by: Yajun Wu <yaj...@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c |  7 +++++++
 drivers/common/mlx5/mlx5_prm.h       | 17 +++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c 
b/drivers/common/mlx5/mlx5_devx_cmds.c
index d02ac2a678..a2943c9a58 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -2255,11 +2255,13 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 
uint32_t qp_st_mod_op,
                uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
                uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
                uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
+               uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)];
        } in;
        union {
                uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
                uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
                uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
+               uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)];
        } out;
        void *qpc;
        int ret;
@@ -2302,6 +2304,11 @@ mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 
uint32_t qp_st_mod_op,
                inlen = sizeof(in.rtr2rts);
                outlen = sizeof(out.rtr2rts);
                break;
+       case MLX5_CMD_OP_QP_2RST:
+               MLX5_SET(2rst_qp_in, &in, qpn, qp->id);
+               inlen = sizeof(in.qp2rst);
+               outlen = sizeof(out.qp2rst);
+               break;
        default:
                DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
                        qp_st_mod_op);
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 44b18225f6..cca6bfc6d4 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -3653,6 +3653,23 @@ struct mlx5_ifc_init2init_qp_in_bits {
        u8 reserved_at_800[0x80];
 };
 
+struct mlx5_ifc_2rst_qp_out_bits {
+       u8 status[0x8];
+       u8 reserved_at_8[0x18];
+       u8 syndrome[0x20];
+       u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_2rst_qp_in_bits {
+       u8 opcode[0x10];
+       u8 uid[0x10];
+       u8 vhca_tunnel_id[0x10];
+       u8 op_mod[0x10];
+       u8 reserved_at_80[0x8];
+       u8 qpn[0x18];
+       u8 reserved_at_a0[0x20];
+};
+
 struct mlx5_ifc_dealloc_pd_out_bits {
        u8 status[0x8];
        u8 reserved_0[0x18];
-- 
2.27.0