> -----Original Message-----
> From: dev [mailto:dev-bounces at dpdk.org] On Behalf Of
> xuelin.shi at freescale.com
> Sent: Thursday, February 12, 2015 9:20 AM
> To: thomas.monjalon at 6wind.com
> Cc: dev at dpdk.org
> Subject: [dpdk-dev] [PATCH] ixgbe: fix ixgbe PCI access endian issue
>
> From: Xuelin Shi <xuelin.shi at freescale.com>
>
> ixgbe is little endian, but cpu maybe not.
> add necessary conversions.
> rte_cpu_to_le_32(...) for PCI write
> rte_le_to_cpu_32(...) for PCI read.
>
> Signed-off-by: Xuelin Shi <xuelin.shi at freescale.com>
Acked-by: Helin Zhang <helin.zhang at intel.com>
> ---
> lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
> b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
> index 2d40bfd..f8bfb3f 100644
> --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
> +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h
> @@ -119,11 +119,11 @@ typedef int bool;
>
> static inline uint32_t ixgbe_read_addr(volatile void* addr) {
> - return IXGBE_PCI_REG(addr);
> + return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
> }
>
> #define IXGBE_PCI_REG_WRITE(reg, value) do { \
> - IXGBE_PCI_REG((reg)) = (value); \
> + IXGBE_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \
> } while(0)
>
> #define IXGBE_PCI_REG_ADDR(hw, reg) \
> --
> 1.9.1
