Add CNF95xx B0 variant to the list of supported models.
Signed-off-by: Tomasz Duszynski <tduszyn...@marvell.com>
Reviewed-by: Jerin Jacob <jer...@marvell.com>
---
v2:
- Update release notes for new device support (Ferruh)
doc/guides/rel_notes/release_22_03.rst | 1 +
drivers/common/cnxk/roc_model.c | 1 +
drivers/common/cnxk/roc_model.h | 6 ++++--
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/doc/guides/rel_notes/release_22_03.rst
b/doc/guides/rel_notes/release_22_03.rst
index 54563106d1..43c4db65c3 100644
--- a/doc/guides/rel_notes/release_22_03.rst
+++ b/doc/guides/rel_notes/release_22_03.rst
@@ -135,6 +135,7 @@ New Features
* Added queue based priority flow control support for CN9K & CN10K.
* Added support for IP reassembly for inline inbound IPsec packets.
* Added support for packet marking in traffic manager.
+ * Added support for CNF95xx B0 variant SoC.
* **Added an API for private user data in asymmetric crypto session.**
diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c
index 49617c02b7..4120029541 100644
--- a/drivers/common/cnxk/roc_model.c
+++ b/drivers/common/cnxk/roc_model.c
@@ -56,6 +56,7 @@ static const struct model_db {
{VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"},
{VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"},
{VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"},
+ {VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"},
{VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"},
{VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0,
"cnf95xxmm_a0"}};
diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h
index cee06779bc..4567566169 100644
--- a/drivers/common/cnxk/roc_model.h
+++ b/drivers/common/cnxk/roc_model.h
@@ -19,6 +19,7 @@ struct roc_model {
#define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12)
#define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13)
#define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14)
+#define ROC_MODEL_CNF95xxN_B0 BIT_ULL(15)
#define ROC_MODEL_CN98xx_A0 BIT_ULL(16)
#define ROC_MODEL_CN106xx_A0 BIT_ULL(20)
#define ROC_MODEL_CNF105xx_A0 BIT_ULL(21)
@@ -39,11 +40,12 @@ struct roc_model {
(ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \
ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \
ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \
- ROC_MODEL_CNF95xxN_A1)
+ ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0)
#define ROC_MODEL_CNF9K
\
(ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 | \
ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 | \
- ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1)
+ ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 | \
+ ROC_MODEL_CNF95xxN_B0)
#define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0)
#define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0)
--
2.35.1
