On Thu, Jan 20, 2022 at 3:21 PM Jerin Jacob <jerinjac...@gmail.com> wrote:
>
> On Tue, Dec 14, 2021 at 2:53 PM Ruifeng Wang <ruifeng.w...@arm.com> wrote:
> >
> > > -----Original Message-----
> > > From: pbhagavat...@marvell.com <pbhagavat...@marvell.com>
> > > Sent: Monday, December 13, 2021 7:06 PM
> > > To: jer...@marvell.com; Jan Viktorin <vikto...@rehivetech.com>; Ruifeng
> > > Wang <ruifeng.w...@arm.com>; Bruce Richardson
> > > <bruce.richard...@intel.com>
> > > Cc: dev@dpdk.org; Pavan Nikhilesh <pbhagavat...@marvell.com>
> > > Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes
> > >
> > > From: Pavan Nikhilesh <pbhagavat...@marvell.com>
> > >
> > > Mempool elements are by default aligned to CACHELINE_SIZE.
> > > In CN10K cacheline size is 64B but the RoC requires buffers to be aligned
> > > to
> > > 128B.
> > > Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
> > > 128 bytes.
> > >
> > > Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com>
> > > ---
> > > config/arm/meson.build | 3 ++-
> > > 1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > > 213324d262..33afe1a9ad 100644
> > > --- a/config/arm/meson.build
> > > +++ b/config/arm/meson.build
> > > @@ -276,7 +276,8 @@ soc_cn10k = {
> > > 'implementer' : '0x41',
> > > 'flags': [
> > > ['RTE_MAX_LCORE', 24],
> > > - ['RTE_MAX_NUMA_NODES', 1]
> > > + ['RTE_MAX_NUMA_NODES', 1],
> > > + ['RTE_MEMPOOL_ALIGN', 128]
> > > ],
> > > 'part_number': '0xd49',
> > > 'extra_march_features': ['crypto'],
> > > --
> > > 2.17.1
> >
> > Reviewed-by: Ruifeng Wang <ruifeng.w...@arm.com>
>
> Applied to dpdk-next-net-mrvl/for-next-net. Thanks
As per @Ferruh Yigit suggestion, This patch will be taken through the
main tree.
I changed state as New and Delegate as @Thomas Monjalon for this patch in pw.
>
>
> Added
> Fixes: 1b4c86a721c9 ("config/arm: add Marvell CN10K")
> Cc: sta...@dpdk.org
> >
