On Tue, Nov 30, 2021 at 11:11 AM Ashwin Sekhar T K <asek...@marvell.com> wrote:
>
> When PLT_CACHE_LINE_SIZE is set to 64B, the memzone size reserved for
> NPA stack could be a multiple of 64B. In such a case, when NDC SYNC
> is initiated for the NPA LF, it could go and corrupt an additional
> 64B bytes as NDC flushes in multiples of ROC cache line size (128B).
>
> So ensure that NPA stack size requested is a multiple of 128B.
>
> Signed-off-by: Ashwin Sekhar T K <asek...@marvell.com>
Acked-by: Jerin Jacob <jer...@marvell.com>
Applied to dpdk-next-net-mrvl/for-next-net. Thanks
> ---
> drivers/common/cnxk/roc_npa.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
> index efcb7582eb..75fc22442f 100644
> --- a/drivers/common/cnxk/roc_npa.c
> +++ b/drivers/common/cnxk/roc_npa.c
> @@ -205,6 +205,7 @@ static inline const struct plt_memzone *
> npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
> {
> const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
> + size = PLT_ALIGN_CEIL(size, ROC_ALIGN);
>
> return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
> }
> --
> 2.32.0
>
