From: Nipun Gupta <nipun.gu...@nxp.com> Outer Shareable Store (oshst) is sufficient for Data Memory Barrier (dmb) when doing IO on the interface via QBMAN.
This will sync L3/DDR with the L1/L2 cached data. Signed-off-by: Nipun Gupta <nipun.gu...@nxp.com> --- drivers/bus/fslmc/qbman/include/compat.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/bus/fslmc/qbman/include/compat.h b/drivers/bus/fslmc/qbman/include/compat.h index a4471a80af..ece5da5906 100644 --- a/drivers/bus/fslmc/qbman/include/compat.h +++ b/drivers/bus/fslmc/qbman/include/compat.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2008-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017,2021 NXP * */ @@ -81,7 +81,7 @@ do { \ #define __raw_readl(p) (*(const volatile unsigned int *)(p)) #define __raw_writel(v, p) {*(volatile unsigned int *)(p) = (v); } -#define dma_wmb() rte_smp_mb() +#define dma_wmb() rte_io_wmb() #define atomic_t rte_atomic32_t #define atomic_read(v) rte_atomic32_read(v) -- 2.17.1