Initialising mlx5 devices in OVS, I get the following logs:
2021-11-16T20:08:37Z|00021|dpdk|INFO|EAL: Probe PCI driver: mlx5_pci
(15b3:101d) device: 0000:3b:00.0 (socket 0)
2021-11-16T20:08:37Z|00022|dpdk|INFO|common_mlx5: RTE_MEM is selected.
2021-11-16T20:08:38Z|00023|dpdk|WARN|mlx5_pci: Size 0xFFFF is not power
of 2, will be aligned to 0x10000.
Those logs just make no sense for a final user and were raised to WARN
level recently.
Lower them back to DEBUG.
Fixes: 961b6774c451 ("common/mlx5: add per-lcore cache to hash list utility")
Signed-off-by: David Marchand <david.march...@redhat.com>
---
drivers/common/mlx5/mlx5_common_utils.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/mlx5/mlx5_common_utils.c
b/drivers/common/mlx5/mlx5_common_utils.c
index 775fabd478..c83333b4b4 100644
--- a/drivers/common/mlx5/mlx5_common_utils.c
+++ b/drivers/common/mlx5/mlx5_common_utils.c
@@ -406,7 +406,7 @@ mlx5_hlist_create(const char *name, uint32_t size, bool
direct_key,
/* Align to the next power of 2, 32bits integer is enough now. */
if (!rte_is_power_of_2(size)) {
act_size = rte_align32pow2(size);
- DRV_LOG(WARNING, "Size 0x%" PRIX32 " is not power of 2, will "
+ DRV_LOG(DEBUG, "Size 0x%" PRIX32 " is not power of 2, will "
"be aligned to 0x%" PRIX32 ".", size, act_size);
} else {
act_size = size;
--
2.23.0
