> -----Original Message-----
> From: fengchengwen <fengcheng...@huawei.com>
> Sent: Tuesday, November 2, 2021 3:01 PM
> To: Gagandeep Singh <g.si...@nxp.com>; tho...@monjalon.net;
> dev@dpdk.org
> Cc: Nipun Gupta <nipun.gu...@nxp.com>
> Subject: Re: [dpdk-dev] [PATCH v2 5/6] dma/dpaa: support DMA operations
>
> On 2021/11/1 16:51, Gagandeep Singh wrote:
> > This patch support copy, submit, completed and
> > completed status functionality of DMA driver.
> >
> > Signed-off-by: Gagandeep Singh <g.si...@nxp.com>
>
> ...
>
> > +
> > +static int fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan,
> > + struct fsl_qdma_comp *fsl_comp,
> > + uint64_t flags)
> > +{
> > + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
> > + void *block = fsl_queue->block_base;
> > + struct fsl_qdma_format *ccdf;
> > + u32 reg;
> > +
> > + /* retrieve and store the register value in big endian
> > + * to avoid bits swap
> > + */
> > + reg = qdma_readl_be(block +
> > + FSL_QDMA_BCQSR(fsl_queue->id));
> > + if (reg & (FSL_QDMA_BCQSR_QF_XOFF_BE))
> > + return -1;
> > +
> > + /* filling descriptor command table */
> > + ccdf = (struct fsl_qdma_format *)fsl_queue->virt_head;
> > + qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
> > + qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(fsl_comp-
> >virt_addr));
> > + qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(fsl_comp->virt_addr));
> > + fsl_comp->index = fsl_queue->virt_head - fsl_queue->cq;
> > + fsl_queue->virt_head++;
> > +
> > + if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)
> > + fsl_queue->virt_head = fsl_queue->cq;
> > +
> > + list_add_tail(&fsl_comp->list, &fsl_queue->comp_used);
> > +
> > + if (flags == RTE_DMA_OP_FLAG_SUBMIT) {
> > + reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue-
> >id));
> > + reg |= FSL_QDMA_BCQMR_EI_BE;
> > + qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue-
> >id));
> > + }
> > + return fsl_comp->index;
>
> I can't catch the index real range? it should to be [0, 0xffff] from framework
> view.
Index range is [0, 63]. It depends upon the fsl_queue->n_cq which is configured
as QDMA_QUEUE_SIZE.
>
> > +}
> > +
> > static int fsl_qdma_alloc_chan_resources(struct fsl_qdma_chan *fsl_chan)
> > {
> > struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
> > @@ -492,6 +690,148 @@ dpaa_qdma_queue_setup(struct rte_dma_dev
> *dmadev,
> > return dpaa_get_channel(fsl_qdma, vchan);
> > }
> >
> > +static int
> > +dpaa_qdma_submit(void *dev_private, uint16_t vchan)
> > +{
> > + struct fsl_qdma_engine *fsl_qdma = (struct fsl_qdma_engine
> *)dev_private;
> > + struct fsl_qdma_chan *fsl_chan =
> > + &fsl_qdma->chans[fsl_qdma->vchan_map[vchan]];
> > + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
> > + void *block = fsl_queue->block_base;
> > + u32 reg;
> > +
> > + reg = qdma_readl_be(block + FSL_QDMA_BCQMR(fsl_queue->id));
> > + reg |= FSL_QDMA_BCQMR_EI_BE;
> > + qdma_writel_be(reg, block + FSL_QDMA_BCQMR(fsl_queue->id));
> > +
> > + return 0;
> > +}
> > +
>
> ...
>
> >
> >
