On 3/5/2015 9:24 PM, Richardson, Bruce wrote:
> On Thu, Mar 05, 2015 at 09:15:39PM +0800, Michael Qiu wrote:
>> include/rte_cpuflags.h:154:2: error: redeclaration of enumerator ?REG_EAX?
>> In file included from /usr/include/signal.h:358:0,
>> from /usr/include/sys/wait.h:30,
>> from /root/dpdk/app/test/test_mp_secondary.c:50:
>> /usr/include/sys/ucontext.h:180:3: note: previous definition of ?REG_EAX?
>> was here
>>
>> In i686, from REG_EAX to REG_EDX are all defined in
>> /usr/include/sys/ucontext.h
>>
>> Rename to CPU_REG_EAX to avoid this issue.
> RTE_ prefix for consistency with other public DPDK symbols perhaps?
Hi, Bruce
Yes, agree.
I will send out v2 now.
Thanks,
Michael
> /Bruce
>
>> Signed-off-by: Michael Qou <michael.qiu at intel.com>
>> ---
>> .../common/include/arch/x86/rte_cpuflags.h | 210
>> ++++++++++-----------
>> 1 file changed, 105 insertions(+), 105 deletions(-)
>>
>> diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
>> b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
>> index a58dd7b..f367b91 100644
>> --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
>> +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
>> @@ -151,104 +151,104 @@ enum rte_cpu_flag_t {
>> };
>>
>> enum cpu_register_t {
>> - REG_EAX = 0,
>> - REG_EBX,
>> - REG_ECX,
>> - REG_EDX,
>> + CPU_REG_EAX = 0,
>> + CPU_REG_EBX,
>> + CPU_REG_ECX,
>> + CPU_REG_EDX,
>> };
>>
>> static const struct feature_entry cpu_feature_table[] = {
>> - FEAT_DEF(SSE3, 0x00000001, 0, REG_ECX, 0)
>> - FEAT_DEF(PCLMULQDQ, 0x00000001, 0, REG_ECX, 1)
>> - FEAT_DEF(DTES64, 0x00000001, 0, REG_ECX, 2)
>> - FEAT_DEF(MONITOR, 0x00000001, 0, REG_ECX, 3)
>> - FEAT_DEF(DS_CPL, 0x00000001, 0, REG_ECX, 4)
>> - FEAT_DEF(VMX, 0x00000001, 0, REG_ECX, 5)
>> - FEAT_DEF(SMX, 0x00000001, 0, REG_ECX, 6)
>> - FEAT_DEF(EIST, 0x00000001, 0, REG_ECX, 7)
>> - FEAT_DEF(TM2, 0x00000001, 0, REG_ECX, 8)
>> - FEAT_DEF(SSSE3, 0x00000001, 0, REG_ECX, 9)
>> - FEAT_DEF(CNXT_ID, 0x00000001, 0, REG_ECX, 10)
>> - FEAT_DEF(FMA, 0x00000001, 0, REG_ECX, 12)
>> - FEAT_DEF(CMPXCHG16B, 0x00000001, 0, REG_ECX, 13)
>> - FEAT_DEF(XTPR, 0x00000001, 0, REG_ECX, 14)
>> - FEAT_DEF(PDCM, 0x00000001, 0, REG_ECX, 15)
>> - FEAT_DEF(PCID, 0x00000001, 0, REG_ECX, 17)
>> - FEAT_DEF(DCA, 0x00000001, 0, REG_ECX, 18)
>> - FEAT_DEF(SSE4_1, 0x00000001, 0, REG_ECX, 19)
>> - FEAT_DEF(SSE4_2, 0x00000001, 0, REG_ECX, 20)
>> - FEAT_DEF(X2APIC, 0x00000001, 0, REG_ECX, 21)
>> - FEAT_DEF(MOVBE, 0x00000001, 0, REG_ECX, 22)
>> - FEAT_DEF(POPCNT, 0x00000001, 0, REG_ECX, 23)
>> - FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, REG_ECX, 24)
>> - FEAT_DEF(AES, 0x00000001, 0, REG_ECX, 25)
>> - FEAT_DEF(XSAVE, 0x00000001, 0, REG_ECX, 26)
>> - FEAT_DEF(OSXSAVE, 0x00000001, 0, REG_ECX, 27)
>> - FEAT_DEF(AVX, 0x00000001, 0, REG_ECX, 28)
>> - FEAT_DEF(F16C, 0x00000001, 0, REG_ECX, 29)
>> - FEAT_DEF(RDRAND, 0x00000001, 0, REG_ECX, 30)
>> -
>> - FEAT_DEF(FPU, 0x00000001, 0, REG_EDX, 0)
>> - FEAT_DEF(VME, 0x00000001, 0, REG_EDX, 1)
>> - FEAT_DEF(DE, 0x00000001, 0, REG_EDX, 2)
>> - FEAT_DEF(PSE, 0x00000001, 0, REG_EDX, 3)
>> - FEAT_DEF(TSC, 0x00000001, 0, REG_EDX, 4)
>> - FEAT_DEF(MSR, 0x00000001, 0, REG_EDX, 5)
>> - FEAT_DEF(PAE, 0x00000001, 0, REG_EDX, 6)
>> - FEAT_DEF(MCE, 0x00000001, 0, REG_EDX, 7)
>> - FEAT_DEF(CX8, 0x00000001, 0, REG_EDX, 8)
>> - FEAT_DEF(APIC, 0x00000001, 0, REG_EDX, 9)
>> - FEAT_DEF(SEP, 0x00000001, 0, REG_EDX, 11)
>> - FEAT_DEF(MTRR, 0x00000001, 0, REG_EDX, 12)
>> - FEAT_DEF(PGE, 0x00000001, 0, REG_EDX, 13)
>> - FEAT_DEF(MCA, 0x00000001, 0, REG_EDX, 14)
>> - FEAT_DEF(CMOV, 0x00000001, 0, REG_EDX, 15)
>> - FEAT_DEF(PAT, 0x00000001, 0, REG_EDX, 16)
>> - FEAT_DEF(PSE36, 0x00000001, 0, REG_EDX, 17)
>> - FEAT_DEF(PSN, 0x00000001, 0, REG_EDX, 18)
>> - FEAT_DEF(CLFSH, 0x00000001, 0, REG_EDX, 19)
>> - FEAT_DEF(DS, 0x00000001, 0, REG_EDX, 21)
>> - FEAT_DEF(ACPI, 0x00000001, 0, REG_EDX, 22)
>> - FEAT_DEF(MMX, 0x00000001, 0, REG_EDX, 23)
>> - FEAT_DEF(FXSR, 0x00000001, 0, REG_EDX, 24)
>> - FEAT_DEF(SSE, 0x00000001, 0, REG_EDX, 25)
>> - FEAT_DEF(SSE2, 0x00000001, 0, REG_EDX, 26)
>> - FEAT_DEF(SS, 0x00000001, 0, REG_EDX, 27)
>> - FEAT_DEF(HTT, 0x00000001, 0, REG_EDX, 28)
>> - FEAT_DEF(TM, 0x00000001, 0, REG_EDX, 29)
>> - FEAT_DEF(PBE, 0x00000001, 0, REG_EDX, 31)
>> -
>> - FEAT_DEF(DIGTEMP, 0x00000006, 0, REG_EAX, 0)
>> - FEAT_DEF(TRBOBST, 0x00000006, 0, REG_EAX, 1)
>> - FEAT_DEF(ARAT, 0x00000006, 0, REG_EAX, 2)
>> - FEAT_DEF(PLN, 0x00000006, 0, REG_EAX, 4)
>> - FEAT_DEF(ECMD, 0x00000006, 0, REG_EAX, 5)
>> - FEAT_DEF(PTM, 0x00000006, 0, REG_EAX, 6)
>> -
>> - FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, REG_ECX, 0)
>> - FEAT_DEF(ACNT2, 0x00000006, 0, REG_ECX, 1)
>> - FEAT_DEF(ENERGY_EFF, 0x00000006, 0, REG_ECX, 3)
>> -
>> - FEAT_DEF(FSGSBASE, 0x00000007, 0, REG_EBX, 0)
>> - FEAT_DEF(BMI1, 0x00000007, 0, REG_EBX, 2)
>> - FEAT_DEF(HLE, 0x00000007, 0, REG_EBX, 4)
>> - FEAT_DEF(AVX2, 0x00000007, 0, REG_EBX, 5)
>> - FEAT_DEF(SMEP, 0x00000007, 0, REG_EBX, 6)
>> - FEAT_DEF(BMI2, 0x00000007, 0, REG_EBX, 7)
>> - FEAT_DEF(ERMS, 0x00000007, 0, REG_EBX, 8)
>> - FEAT_DEF(INVPCID, 0x00000007, 0, REG_EBX, 10)
>> - FEAT_DEF(RTM, 0x00000007, 0, REG_EBX, 11)
>> -
>> - FEAT_DEF(LAHF_SAHF, 0x80000001, 0, REG_ECX, 0)
>> - FEAT_DEF(LZCNT, 0x80000001, 0, REG_ECX, 4)
>> -
>> - FEAT_DEF(SYSCALL, 0x80000001, 0, REG_EDX, 11)
>> - FEAT_DEF(XD, 0x80000001, 0, REG_EDX, 20)
>> - FEAT_DEF(1GB_PG, 0x80000001, 0, REG_EDX, 26)
>> - FEAT_DEF(RDTSCP, 0x80000001, 0, REG_EDX, 27)
>> - FEAT_DEF(EM64T, 0x80000001, 0, REG_EDX, 29)
>> -
>> - FEAT_DEF(INVTSC, 0x80000007, 0, REG_EDX, 8)
>> + FEAT_DEF(SSE3, 0x00000001, 0, CPU_REG_ECX, 0)
>> + FEAT_DEF(PCLMULQDQ, 0x00000001, 0, CPU_REG_ECX, 1)
>> + FEAT_DEF(DTES64, 0x00000001, 0, CPU_REG_ECX, 2)
>> + FEAT_DEF(MONITOR, 0x00000001, 0, CPU_REG_ECX, 3)
>> + FEAT_DEF(DS_CPL, 0x00000001, 0, CPU_REG_ECX, 4)
>> + FEAT_DEF(VMX, 0x00000001, 0, CPU_REG_ECX, 5)
>> + FEAT_DEF(SMX, 0x00000001, 0, CPU_REG_ECX, 6)
>> + FEAT_DEF(EIST, 0x00000001, 0, CPU_REG_ECX, 7)
>> + FEAT_DEF(TM2, 0x00000001, 0, CPU_REG_ECX, 8)
>> + FEAT_DEF(SSSE3, 0x00000001, 0, CPU_REG_ECX, 9)
>> + FEAT_DEF(CNXT_ID, 0x00000001, 0, CPU_REG_ECX, 10)
>> + FEAT_DEF(FMA, 0x00000001, 0, CPU_REG_ECX, 12)
>> + FEAT_DEF(CMPXCHG16B, 0x00000001, 0, CPU_REG_ECX, 13)
>> + FEAT_DEF(XTPR, 0x00000001, 0, CPU_REG_ECX, 14)
>> + FEAT_DEF(PDCM, 0x00000001, 0, CPU_REG_ECX, 15)
>> + FEAT_DEF(PCID, 0x00000001, 0, CPU_REG_ECX, 17)
>> + FEAT_DEF(DCA, 0x00000001, 0, CPU_REG_ECX, 18)
>> + FEAT_DEF(SSE4_1, 0x00000001, 0, CPU_REG_ECX, 19)
>> + FEAT_DEF(SSE4_2, 0x00000001, 0, CPU_REG_ECX, 20)
>> + FEAT_DEF(X2APIC, 0x00000001, 0, CPU_REG_ECX, 21)
>> + FEAT_DEF(MOVBE, 0x00000001, 0, CPU_REG_ECX, 22)
>> + FEAT_DEF(POPCNT, 0x00000001, 0, CPU_REG_ECX, 23)
>> + FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, CPU_REG_ECX, 24)
>> + FEAT_DEF(AES, 0x00000001, 0, CPU_REG_ECX, 25)
>> + FEAT_DEF(XSAVE, 0x00000001, 0, CPU_REG_ECX, 26)
>> + FEAT_DEF(OSXSAVE, 0x00000001, 0, CPU_REG_ECX, 27)
>> + FEAT_DEF(AVX, 0x00000001, 0, CPU_REG_ECX, 28)
>> + FEAT_DEF(F16C, 0x00000001, 0, CPU_REG_ECX, 29)
>> + FEAT_DEF(RDRAND, 0x00000001, 0, CPU_REG_ECX, 30)
>> +
>> + FEAT_DEF(FPU, 0x00000001, 0, CPU_REG_EDX, 0)
>> + FEAT_DEF(VME, 0x00000001, 0, CPU_REG_EDX, 1)
>> + FEAT_DEF(DE, 0x00000001, 0, CPU_REG_EDX, 2)
>> + FEAT_DEF(PSE, 0x00000001, 0, CPU_REG_EDX, 3)
>> + FEAT_DEF(TSC, 0x00000001, 0, CPU_REG_EDX, 4)
>> + FEAT_DEF(MSR, 0x00000001, 0, CPU_REG_EDX, 5)
>> + FEAT_DEF(PAE, 0x00000001, 0, CPU_REG_EDX, 6)
>> + FEAT_DEF(MCE, 0x00000001, 0, CPU_REG_EDX, 7)
>> + FEAT_DEF(CX8, 0x00000001, 0, CPU_REG_EDX, 8)
>> + FEAT_DEF(APIC, 0x00000001, 0, CPU_REG_EDX, 9)
>> + FEAT_DEF(SEP, 0x00000001, 0, CPU_REG_EDX, 11)
>> + FEAT_DEF(MTRR, 0x00000001, 0, CPU_REG_EDX, 12)
>> + FEAT_DEF(PGE, 0x00000001, 0, CPU_REG_EDX, 13)
>> + FEAT_DEF(MCA, 0x00000001, 0, CPU_REG_EDX, 14)
>> + FEAT_DEF(CMOV, 0x00000001, 0, CPU_REG_EDX, 15)
>> + FEAT_DEF(PAT, 0x00000001, 0, CPU_REG_EDX, 16)
>> + FEAT_DEF(PSE36, 0x00000001, 0, CPU_REG_EDX, 17)
>> + FEAT_DEF(PSN, 0x00000001, 0, CPU_REG_EDX, 18)
>> + FEAT_DEF(CLFSH, 0x00000001, 0, CPU_REG_EDX, 19)
>> + FEAT_DEF(DS, 0x00000001, 0, CPU_REG_EDX, 21)
>> + FEAT_DEF(ACPI, 0x00000001, 0, CPU_REG_EDX, 22)
>> + FEAT_DEF(MMX, 0x00000001, 0, CPU_REG_EDX, 23)
>> + FEAT_DEF(FXSR, 0x00000001, 0, CPU_REG_EDX, 24)
>> + FEAT_DEF(SSE, 0x00000001, 0, CPU_REG_EDX, 25)
>> + FEAT_DEF(SSE2, 0x00000001, 0, CPU_REG_EDX, 26)
>> + FEAT_DEF(SS, 0x00000001, 0, CPU_REG_EDX, 27)
>> + FEAT_DEF(HTT, 0x00000001, 0, CPU_REG_EDX, 28)
>> + FEAT_DEF(TM, 0x00000001, 0, CPU_REG_EDX, 29)
>> + FEAT_DEF(PBE, 0x00000001, 0, CPU_REG_EDX, 31)
>> +
>> + FEAT_DEF(DIGTEMP, 0x00000006, 0, CPU_REG_EAX, 0)
>> + FEAT_DEF(TRBOBST, 0x00000006, 0, CPU_REG_EAX, 1)
>> + FEAT_DEF(ARAT, 0x00000006, 0, CPU_REG_EAX, 2)
>> + FEAT_DEF(PLN, 0x00000006, 0, CPU_REG_EAX, 4)
>> + FEAT_DEF(ECMD, 0x00000006, 0, CPU_REG_EAX, 5)
>> + FEAT_DEF(PTM, 0x00000006, 0, CPU_REG_EAX, 6)
>> +
>> + FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, CPU_REG_ECX, 0)
>> + FEAT_DEF(ACNT2, 0x00000006, 0, CPU_REG_ECX, 1)
>> + FEAT_DEF(ENERGY_EFF, 0x00000006, 0, CPU_REG_ECX, 3)
>> +
>> + FEAT_DEF(FSGSBASE, 0x00000007, 0, CPU_REG_EBX, 0)
>> + FEAT_DEF(BMI1, 0x00000007, 0, CPU_REG_EBX, 2)
>> + FEAT_DEF(HLE, 0x00000007, 0, CPU_REG_EBX, 4)
>> + FEAT_DEF(AVX2, 0x00000007, 0, CPU_REG_EBX, 5)
>> + FEAT_DEF(SMEP, 0x00000007, 0, CPU_REG_EBX, 6)
>> + FEAT_DEF(BMI2, 0x00000007, 0, CPU_REG_EBX, 7)
>> + FEAT_DEF(ERMS, 0x00000007, 0, CPU_REG_EBX, 8)
>> + FEAT_DEF(INVPCID, 0x00000007, 0, CPU_REG_EBX, 10)
>> + FEAT_DEF(RTM, 0x00000007, 0, CPU_REG_EBX, 11)
>> +
>> + FEAT_DEF(LAHF_SAHF, 0x80000001, 0, CPU_REG_ECX, 0)
>> + FEAT_DEF(LZCNT, 0x80000001, 0, CPU_REG_ECX, 4)
>> +
>> + FEAT_DEF(SYSCALL, 0x80000001, 0, CPU_REG_EDX, 11)
>> + FEAT_DEF(XD, 0x80000001, 0, CPU_REG_EDX, 20)
>> + FEAT_DEF(1GB_PG, 0x80000001, 0, CPU_REG_EDX, 26)
>> + FEAT_DEF(RDTSCP, 0x80000001, 0, CPU_REG_EDX, 27)
>> + FEAT_DEF(EM64T, 0x80000001, 0, CPU_REG_EDX, 29)
>> +
>> + FEAT_DEF(INVTSC, 0x80000007, 0, CPU_REG_EDX, 8)
>> };
>>
>> static inline void
>> @@ -257,18 +257,18 @@ rte_cpu_get_features(uint32_t leaf, uint32_t subleaf,
>> cpuid_registers_t out)
>> #if defined(__i386__) && defined(__PIC__)
>> /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
>> asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
>> - : "=r" (out[REG_EBX]),
>> - "=a" (out[REG_EAX]),
>> - "=c" (out[REG_ECX]),
>> - "=d" (out[REG_EDX])
>> + : "=r" (out[CPU_REG_EBX]),
>> + "=a" (out[CPU_REG_EAX]),
>> + "=c" (out[CPU_REG_ECX]),
>> + "=d" (out[CPU_REG_EDX])
>> : "a" (leaf), "c" (subleaf));
>> #else
>>
>> asm volatile("cpuid"
>> - : "=a" (out[REG_EAX]),
>> - "=b" (out[REG_EBX]),
>> - "=c" (out[REG_ECX]),
>> - "=d" (out[REG_EDX])
>> + : "=a" (out[CPU_REG_EAX]),
>> + "=b" (out[CPU_REG_EBX]),
>> + "=c" (out[CPU_REG_ECX]),
>> + "=d" (out[CPU_REG_EDX])
>> : "a" (leaf), "c" (subleaf));
>>
>> #endif
>> @@ -292,8 +292,8 @@ rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
>> return -EFAULT;
>>
>> rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
>> - if (((regs[REG_EAX] ^ feat->leaf) & 0xffff0000) ||
>> - regs[REG_EAX] < feat->leaf)
>> + if (((regs[CPU_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
>> + regs[CPU_REG_EAX] < feat->leaf)
>> return 0;
>>
>> /* get the cpuid leaf containing the desired feature */
>> --
>> 1.9.3
>>
