From: Michael Shamis <michae...@marvell.com>
Till now comments explain queue mapping per
one and two crypto devices.
Now added comments for queue mapping for three
crypto devices supported in CN9132.
Signed-off-by: Michael Shamis <michae...@marvell.com>
Reviewed-by: Liron Himi <lir...@marvell.com>
---
drivers/crypto/mvsam/rte_mrvl_pmd_ops.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/mvsam/rte_mrvl_pmd_ops.c
b/drivers/crypto/mvsam/rte_mrvl_pmd_ops.c
index 1a0a9fc14..75bb8adb8 100644
--- a/drivers/crypto/mvsam/rte_mrvl_pmd_ops.c
+++ b/drivers/crypto/mvsam/rte_mrvl_pmd_ops.c
@@ -663,6 +663,11 @@ mrvl_crypto_pmd_qp_setup(struct rte_cryptodev *dev,
uint16_t qp_id,
}
/*
+ * In case just one engine is enabled mapping will look as
+ * follows:
+ * qp: 0 1 2 3
+ * cio-x:y: cio-0:0, cio-0:1, cio-0:2, cio-0:3
+ *
* In case two crypto engines are enabled qps will
* be evenly spread among them. Even and odd qps will
* be handled by cio-0 and cio-1 respectively. qp-cio mapping
@@ -674,10 +679,17 @@ mrvl_crypto_pmd_qp_setup(struct rte_cryptodev *dev,
uint16_t qp_id,
* qp: 4 5 6 7
* cio-x:y: cio-0:2, cio-1:2, cio-0:3, cio-1:3
*
- * In case just one engine is enabled mapping will look as
- * follows:
+ * In case of three crypto engines are enabled qps will
+ * be mapped as following:
+ *
* qp: 0 1 2 3
- * cio-x:y: cio-0:0, cio-0:1, cio-0:2, cio-0:3
+ * cio-x:y: cio-0:0, cio-1:0, cio-2:0, cio-0:1
+ *
+ * qp: 4 5 6 7
+ * cio-x:y: cio-1:1, cio-2:1, cio-0:2, cio-1:2
+ *
+ * qp: 8 9 10 11
+ * cio-x:y: cio-2:2, cio-0:3, cio-1:3, cio-2:3
*/
n = snprintf(match, sizeof(match), "cio-%u:%u",
qp_id % num, qp_id / num);
--
2.17.1
