<snip>
>
> For Arm platforms, reading descs can get re-ordered, then the status of DD
> bits will be discontinuous, so add the logic to only process continuous descs
> by checking DD bits.
>
> Fixes: 4861cde46116 ("i40e: new poll mode driver")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Joyce Kong <joyce.k...@arm.com>
> Reviewed-by: Ruifeng Wang <ruifeng.w...@arm.com>
> ---
> drivers/net/i40e/i40e_rxtx.c | 19 +++++++++++++++----
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index
> 6c58decec..86e2f083e 100644
> --- a/drivers/net/i40e/i40e_rxtx.c
> +++ b/drivers/net/i40e/i40e_rxtx.c
> @@ -452,7 +452,7 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
> uint16_t pkt_len;
> uint64_t qword1;
> uint32_t rx_status;
> - int32_t s[I40E_LOOK_AHEAD], nb_dd;
> + int32_t s[I40E_LOOK_AHEAD], var, nb_dd;
> int32_t i, j, nb_rx = 0;
> uint64_t pkt_flags;
> uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; @@ -482,11
> +482,22 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
> I40E_RXD_QW1_STATUS_SHIFT;
> }
>
> - rte_smp_rmb();
> + /* This barrier is to order loads of different words in the
> descriptor */
> + rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
I think this should go into a separate commit as the following change is
unrelated.
>
> /* Compute how many status bits were set */
> - for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
> - nb_dd += s[j] & (1 <<
> I40E_RX_DESC_STATUS_DD_SHIFT);
> + for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) {
> + var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
> #ifdef
> +RTE_ARCH_ARM
> + /* For Arm platforms, only compute continuous
> status bits */
> + if (var)
> + nb_dd += 1;
> + else
> + break;
> +#else
> + nb_dd += var;
> +#endif
> + }
>
> nb_rx += nb_dd;
>
> --
> 2.17.1
