Support the PMD power management API in MLX5 driver.
The monitor policy of this API puts a CPU core to sleep until
a data in some monitored memory address is changed by the NIC.
Implement the get_monitor_addr function to return an address
of a CQE owner bit to monitor the arrival of a new packet.
Signed-off-by: Alexander Kozyrev <akozy...@nvidia.com>
---
doc/guides/rel_notes/release_21_05.rst | 1 +
drivers/net/mlx5/mlx5.c | 2 ++
drivers/net/mlx5/mlx5_rx.c | 19 +++++++++++++++++++
drivers/net/mlx5/mlx5_rx.h | 1 +
4 files changed, 23 insertions(+)
diff --git a/doc/guides/rel_notes/release_21_05.rst
b/doc/guides/rel_notes/release_21_05.rst
index 133a0dbbf2..6957c5420f 100644
--- a/doc/guides/rel_notes/release_21_05.rst
+++ b/doc/guides/rel_notes/release_21_05.rst
@@ -165,6 +165,7 @@ New Features
* Added support for pre-defined meter policy API.
* Added support for ASO (Advanced Steering Operation) meter.
* Added support for ASO metering by PPS (packet per second).
+ * Added support for the monitor policy of Power Management API.
* **Updated NXP DPAA driver.**
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 19ffa16769..8cd6f1eaee 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1615,6 +1615,7 @@ const struct eth_dev_ops mlx5_dev_ops = {
.hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
.hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
.hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
+ .get_monitor_addr = mlx5_get_monitor_addr,
};
/* Available operations from secondary process. */
@@ -1699,6 +1700,7 @@ const struct eth_dev_ops mlx5_dev_ops_isolate = {
.hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
.hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
.hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
+ .get_monitor_addr = mlx5_get_monitor_addr,
};
/**
diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c
index e9fcb522e2..6cd71a44eb 100644
--- a/drivers/net/mlx5/mlx5_rx.c
+++ b/drivers/net/mlx5/mlx5_rx.c
@@ -269,6 +269,25 @@ mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t
rx_queue_id)
return rx_queue_count(rxq);
}
+int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
+{
+ struct mlx5_rxq_data *rxq = rx_queue;
+ const unsigned int cqe_num = 1 << rxq->cqe_n;
+ const unsigned int cqe_mask = cqe_num - 1;
+ const uint16_t idx = rxq->cq_ci & cqe_num;
+ volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
+
+ if (unlikely(rxq->cqes == NULL)) {
+ rte_errno = EINVAL;
+ return -rte_errno;
+ }
+ pmc->addr = &cqe->op_own;
+ pmc->val = !!idx;
+ pmc->mask = MLX5_CQE_OWNER_MASK;
+ pmc->size = sizeof(uint8_t);
+ return 0;
+}
+
/**
* Translate RX completion flags to packet type.
*
diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h
index d5a2de84d1..1b264e5994 100644
--- a/drivers/net/mlx5/mlx5_rx.h
+++ b/drivers/net/mlx5/mlx5_rx.h
@@ -263,6 +263,7 @@ void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t
queue_id,
struct rte_eth_rxq_info *qinfo);
int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
struct rte_eth_burst_mode *mode);
+int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
/* Vectorized version of mlx5_rx.c */
int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
--
2.18.1
