> -----Original Message-----
> From: Wang, Haiyue <haiyue.w...@intel.com>
> Sent: Tuesday, April 27, 2021 9:39 PM
> To: dev@dpdk.org
> Cc: Zhang, Qi Z <qi.z.zh...@intel.com>; Wang, Liang-min
> <liang-min.w...@intel.com>; david.march...@redhat.com; Wang, Haiyue
> <haiyue.w...@intel.com>; Xing, Beilei <beilei.x...@intel.com>; Guo, Jia
> <jia....@intel.com>
> Subject: [PATCH v4 3/3] net/i40e: enable PCI bus master after reset
>
> The VF reset can be triggerred by the PF reset event, in this case, the PCI
> bus
> master will be cleared, then the VF is not allowed to issue any Memory or I/O
> Requests.
>
> So after the reset event is detected, always enable the PCI bus master.
>
> And align the VF reset event handling in device close module as the AVF driver
> does.
>
> Signed-off-by: Haiyue Wang <haiyue.w...@intel.com>
> ---
> drivers/net/i40e/i40e_ethdev_vf.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/i40e/i40e_ethdev_vf.c
> b/drivers/net/i40e/i40e_ethdev_vf.c
> index 3c258ba7c..8b041e94c 100644
> --- a/drivers/net/i40e/i40e_ethdev_vf.c
> +++ b/drivers/net/i40e/i40e_ethdev_vf.c
> @@ -1212,7 +1212,6 @@ i40evf_check_vf_reset_done(struct rte_eth_dev
> *dev)
> if (i >= MAX_RESET_WAIT_CNT)
> return -1;
>
> - vf->vf_reset = false;
> vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
>
> return 0;
> @@ -1391,6 +1390,7 @@ i40evf_handle_pf_event(struct rte_eth_dev *dev,
> uint8_t *msg,
> switch (pf_msg->event) {
> case VIRTCHNL_EVENT_RESET_IMPENDING:
> PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING
> event");
> + vf->vf_reset = true;
> rte_eth_dev_callback_process(dev,
> RTE_ETH_EVENT_INTR_RESET, NULL);
> break;
> @@ -2487,6 +2487,11 @@ i40evf_dev_close(struct rte_eth_dev *dev)
> i40e_shutdown_adminq(hw);
> i40evf_disable_irq0(hw);
>
> + if (vf->vf_reset)
> + rte_pci_set_bus_master(RTE_ETH_DEV_TO_PCI(dev), true);
> +
> + vf->vf_reset = false;
> +
> rte_free(vf->vf_res);
> vf->vf_res = NULL;
> rte_free(vf->aq_resp);
> --
> 2.31.1
Acked-by: Qi Zhang <qi.z.zh...@intel.com>
