> -----Original Message----- > From: Walsh, Conor <conor.wa...@intel.com> > Sent: Monday, April 26, 2021 6:55 PM > To: hemant.agra...@nxp.com; Jerin Jacob <jerinjac...@gmail.com>; > Ruifeng Wang <ruifeng.w...@arm.com> > Cc: jer...@marvell.com; Yigit, Ferruh <ferruh.yi...@intel.com>; > tho...@monjalon.net; David Marchand <david.march...@redhat.com>; > dpdk-dev <dev@dpdk.org>; nd <n...@arm.com>; Honnappa Nagarahalli > <honnappa.nagaraha...@arm.com> > Subject: RE: [dpdk-dev] [PATCH 4/4] examples/l3fwd: make data struct to be > memory efficient > > <snip> > > >> There are some holes in data struct lcore_conf. The holes are due > > >> to alignment requirement. > > >> > > >> For struct lcore_rx_queue, there is no need to make every element > > >> of this type to be cache line aligned, because the data is not > > >> shared between cores. > > >> > > >> Member len of struct mbuf_table can be moved out. So data can be > > >> packed and there will be no need to load an extra cache line when > > >> mbuf table is empty. > > >> > > >> The change showed slight performance improvement on N1SDP > platform. > > >> > > >> Suggested-by: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com> > > >> > > >> Signed-off-by: Ruifeng Wang <ruifeng.w...@arm.com> > > > This change alone is OK in the octeontx2 platform.(No difference in > > performance) > > > combining with 3/4 shows some regression. Probably is due to > > > prefetch or 128B cache line tuning specifics. > > > > We checked it on Layerscape LS2088A platform. No difference for 1-2 > > core case. However observing ~2% regression for 4-8 cores. > > > > Regards, > > > > Hemant > > > > Hi Ruifeng,
Hi Conor, > > l3fwd will no longer build with this patch as you have changed a struct used > by the FIB lookup method. > This patch will need to be updated to also update the FIB lookup method as > you have done with EM and LPM. Thanks for the comments. I will provide v2 with updates. I'm considering to drop this one in v2 series. > > Thanks, > Conor.
