This adds the support to set 'Bus Master Enable' bit in the PCI command
register.
Signed-off-by: Haiyue Wang <haiyue.w...@intel.com>
Tested-by: Qi Zhang <qi.z.zh...@intel.com>
---
drivers/bus/pci/pci_common.c | 20 ++++++++++++++++++++
drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++
drivers/bus/pci/version.map | 3 +++
lib/pci/rte_pci.h | 4 ++++
4 files changed, 39 insertions(+)
diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
index ee7f96635..b631cb9c7 100644
--- a/drivers/bus/pci/pci_common.c
+++ b/drivers/bus/pci/pci_common.c
@@ -746,6 +746,26 @@ rte_pci_find_ext_capability(struct rte_pci_device *dev,
uint32_t cap)
return 0;
}
+int
+rte_pci_enable_bus_master(struct rte_pci_device *dev)
+{
+ uint16_t cmd;
+
+ if (rte_pci_read_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in reading PCI command register\n");
+ return -1;
+ }
+
+ cmd |= RTE_PCI_COMMAND_MASTER;
+
+ if (rte_pci_write_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in writing PCI command register\n");
+ return -1;
+ }
+
+ return 0;
+}
+
struct rte_pci_bus rte_pci_bus = {
.bus = {
.scan = rte_pci_scan,
diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
index 64886b473..83caf477b 100644
--- a/drivers/bus/pci/rte_bus_pci.h
+++ b/drivers/bus/pci/rte_bus_pci.h
@@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f);
__rte_experimental
off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
+/**
+ * Enables Bus Master for device's PCI command register.
+ *
+ * @param dev
+ * A pointer to rte_pci_device structure.
+ *
+ * @return
+ * 0 on success, -1 on error in PCI config space read/write.
+ */
+__rte_experimental
+int rte_pci_enable_bus_master(struct rte_pci_device *dev);
+
/**
* Register a PCI driver.
*
diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map
index f33ed0abd..9dbec12a0 100644
--- a/drivers/bus/pci/version.map
+++ b/drivers/bus/pci/version.map
@@ -21,4 +21,7 @@ EXPERIMENTAL {
global:
rte_pci_find_ext_capability;
+
+ # added in 21.05
+ rte_pci_enable_bus_master;
};
diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
index a8f8e404a..1f33d687f 100644
--- a/lib/pci/rte_pci.h
+++ b/lib/pci/rte_pci.h
@@ -32,6 +32,10 @@ extern "C" {
#define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
#define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
+#define RTE_PCI_COMMAND 0x04 /* 16 bits */
+
+/* PCI Command Register */
+#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */
/* PCI Express capability registers */
#define RTE_PCI_EXP_DEVCTL 8 /* Device Control */
--
2.31.1
