From: Pavan Nikhilesh <pbhagavat...@marvell.com>
Add config support to cross compile for Marvell CN10K SoC.
Marvell CN10K SoC is based on ARM Neoverse N2 cores.
Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com>
Acked-by: Jerin Jacob <jer...@marvell.com>
---
v2 Changes:
- Rebase with ToT.
config/arm/arm64_cn10k_linux_gcc | 16 ++++++++++++++++
config/arm/meson.build | 12 ++++++++++++
2 files changed, 28 insertions(+)
create mode 100644 config/arm/arm64_cn10k_linux_gcc
diff --git a/config/arm/arm64_cn10k_linux_gcc b/config/arm/arm64_cn10k_linux_gcc
new file mode 100644
index 000000000..a3578c03a
--- /dev/null
+++ b/config/arm/arm64_cn10k_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8.6-a'
+endian = 'little'
+
+[properties]
+platform = 'cn10k'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 86cdb9b53..3368cac85 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -316,10 +316,22 @@ soc_thunderxt88 = {
'part_number': '0xa1'
}
+soc_cn10k = {
+ 'description' : 'Marvell OCTEON 10',
+ 'implementer' : '0x41',
+ 'flags': [
+ ['RTE_MAX_LCORE', 24],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
+ 'part_number': '0xd49',
+ 'numa': false
+}
+
socs = {
'generic': soc_generic,
'armada': soc_armada,
'bluefield': soc_bluefield,
+ 'cn10k' : soc_cn10k,
'dpaa': soc_dpaa,
'emag': soc_emag,
'graviton2': soc_graviton2,
--
2.17.1
