When ASSERT is enabled for compilation, the 2 usages of assert mechanism
in the driver are failed due to typos.
Fix the typos.
Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions")
Fixes: 37862dafcbed ("compress/mlx5: support 32-bit systems")
Reported-by: Viacheslav Ovsiienko <viachesl...@nvidia.com>
Signed-off-by: Matan Azrad <ma...@nvidia.com>
Tested-by: Viacheslav Ovsiienko <viachesl...@nvidia.com>
---
drivers/compress/mlx5/mlx5_compress.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/compress/mlx5/mlx5_compress.c
b/drivers/compress/mlx5/mlx5_compress.c
index b47821a..46255ab 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -614,7 +614,7 @@ struct mlx5_compress_qp {
op->consumed = op->src.length;
op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
MLX5_ASSERT(cqe->byte_cnt ==
- qp->opaque_buf[idx].scattered_length);
+ opaq[idx].scattered_length);
switch (xform->csum_type) {
case RTE_COMP_CHECKSUM_CRC32:
op->output_chksum = (uint64_t)rte_be_to_cpu_32
@@ -731,7 +731,7 @@ struct mlx5_compress_qp {
return -1;
}
priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
- MLX5_ASSERT(qp->uar_addr);
+ MLX5_ASSERT(priv->uar_addr);
#ifndef RTE_ARCH_64
rte_spinlock_init(&priv->uar32_sl);
#endif /* RTE_ARCH_64 */
--
1.8.3.1
