On 2021/1/13 1:37, Maxime Coquelin wrote:
On 10/22/20 5:51 PM, 谢华伟(此时此刻） wrote:
From: "huawei.xhw" <huawei....@alibaba-inc.com>
Legacy virtio-pci only supports PIO BAR resource. As we need to create lots of
virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device. We handles
different type of BAR in the similar way.
In previous implementation, with igb_uio we get PIO address from igb_uio
sysfs entry; with uio_pci_generic, we get PIO address from
/proc/ioports.
For PIO/MMIO RW, there is different path for different drivers and arch.
For VFIO, PIO/MMIO RW is through syscall, which has big performance
issue.
Regarding the performance issue, do you have some numbers to share?
AFAICS, it can only have an impact on performance when interrupt mode is
used or queue notification is enabled.
Does your HW Virtio implementation requires notification?
Yes, hardware needs notification to tell which queue has more buffer.
vhost backend also needs notification when it is not running in polling
mode.
It is easy for software backend to sync with frontend whether it needs
notification through memory but a big burden for hardware.
Anyway, using vfio ioctl isn't needed at all. virtio PMD is only the
consumer of pci_vfio_ioport_read.
we could consider if we still need pci_vfio_ioport_read related API in
future.
/huawei
Is performance the only issue to have your HW working with Virtio PMD,
or is this series also fixing some functionnal issues?
Best regards,
Maxime
