> -----Original Message----- > From: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com> > Sent: Saturday, January 9, 2021 7:58 AM > To: Ruifeng Wang <ruifeng.w...@arm.com>; jer...@marvell.com; Ruifeng > Wang <ruifeng.w...@arm.com>; Jan Viktorin <vikto...@rehivetech.com>; > Bruce Richardson <bruce.richard...@intel.com> > Cc: dev@dpdk.org; vladimir.medved...@intel.com; > hemant.agra...@nxp.com; nd <n...@arm.com>; Honnappa Nagarahalli > <honnappa.nagaraha...@arm.com>; nd <n...@arm.com> > Subject: RE: [PATCH v2 5/5] config: add Arm Neoverse N2 > > + Juraj > > Please note that this clashes with Juraj's patch for meson rework.
Yes. I didn't base it on the build options rework series. I will rebase when that series got merged. > > <snip> > > > > > Add Arm Neoverse N2 cpu support. > > > > Signed-off-by: Ruifeng Wang <ruifeng.w...@arm.com> > > --- > > config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++ > > config/arm/meson.build | 11 ++++++++++- > > 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 > > config/arm/arm64_n2_linux_gcc > > > > diff --git a/config/arm/arm64_n2_linux_gcc > > b/config/arm/arm64_n2_linux_gcc new file mode 100644 index > > 000000000..78f6f3e2b > > --- /dev/null > > +++ b/config/arm/arm64_n2_linux_gcc > > @@ -0,0 +1,17 @@ > > +[binaries] > > +c = 'aarch64-linux-gnu-gcc' > > +cpp = 'aarch64-linux-gnu-cpp' > > +ar = 'aarch64-linux-gnu-gcc-ar' > > +strip = 'aarch64-linux-gnu-strip' > > +pkgconfig = 'aarch64-linux-gnu-pkg-config' > > +pcap-config = '' > > + > > +[host_machine] > > +system = 'linux' > > +cpu_family = 'aarch64' > > +cpu = 'armv8-a' > > +endian = 'little' > > + > > +[properties] > > +implementor_id = '0x41' > > +implementor_pn = '0xd49' > > diff --git a/config/arm/meson.build b/config/arm/meson.build index > > 42b4e43c7..58e0ae643 100644 > > --- a/config/arm/meson.build > > +++ b/config/arm/meson.build > > @@ -89,6 +89,14 @@ flags_n1generic_extra = [ > > ['RTE_MAX_NUMA_NODES', 1], > > ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], > > ['RTE_LIBRTE_VHOST_NUMA', false]] > > +flags_n2generic_extra = [ > > + ['RTE_MACHINE', '"neoverse-n2"'], > > + ['RTE_MAX_LCORE', 64], > > + ['RTE_CACHE_LINE_SIZE', 64], > > + ['RTE_ARM_FEATURE_ATOMICS', true], > > + ['RTE_USE_C11_MEM_MODEL', true], > > + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], > > + ['RTE_LIBRTE_VHOST_NUMA', false]] > Do we need a flag RTE_ARM_FEATURE_SVE? I don't think extra flag is needed. We can rely on __ARM_FEATURE_SVE from compiler. One scenario I can think of where RTE_ARM_FEATURE_SVE can be needed is, when we are writing inline assembly with sve instructions and using compiler that has no sve support. I'm not sure we will have sve inline assembly as C intrinsics are available. > > > > > machine_args_generic = [ > > ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -100,7 > > +108,8 @@ machine_args_generic = [ > > ['0xd09', ['-mcpu=cortex-a73']], > > ['0xd0a', ['-mcpu=cortex-a75']], > > ['0xd0b', ['-mcpu=cortex-a76']], > > - ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], > > flags_n1generic_extra]] > > + ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], > > flags_n1generic_extra], > > + ['0xd49', ['-march=armv8.5-a+crypto+sve'], flags_n2generic_extra]] > Should this be 'sve2'? There should be a flag to indicate SVE2. Yes. N2 supports sve2 and sve2 is superset of sve. I will do the change in next version. > > > > > machine_args_cavium = [ > > ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], > > -- > > 2.25.1
