> -----Original Message-----
> From: Nithin Dabilpuram <ndabilpu...@marvell.com>
> Sent: Monday, December 14, 2020 10:29 AM
> To: Dumitrescu, Cristian <cristian.dumitre...@intel.com>
> Cc: jer...@marvell.com; dev@dpdk.org; Nithin Dabilpuram
> <ndabilpu...@marvell.com>
> Subject: [PATCH 2/2] bitmap: fix bitmap not empty API for 128B cacheline
>
> Currently bitmap line not empty check API assumes cache line
> of 64B and only checks 8 slabs. Since in 128B cacheline, we
> have 16 slabs per cacheline, plt_bitmap_clear() will mark
> complete line as empty as soon as 8 slabs are full thereby
> breaking bitmap scan functionality. Fix it by defining new
> __plt_bitmap_line_not_empty() for 128B cacheline platform.
>
> Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com>
> ---
> lib/librte_eal/include/rte_bitmap.h | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/lib/librte_eal/include/rte_bitmap.h
> b/lib/librte_eal/include/rte_bitmap.h
> index 7c90ef3..d9a1b54 100644
> --- a/lib/librte_eal/include/rte_bitmap.h
> +++ b/lib/librte_eal/include/rte_bitmap.h
> @@ -417,6 +417,7 @@ rte_bitmap_set_slab(struct rte_bitmap *bmp,
> uint32_t pos, uint64_t slab)
> *slab1 |= 1llu << offset1;
> }
>
> +#if RTE_BITMAP_CL_SLAB_SIZE == 8
> static inline uint64_t
> __rte_bitmap_line_not_empty(uint64_t *slab2)
> {
> @@ -432,6 +433,30 @@ __rte_bitmap_line_not_empty(uint64_t *slab2)
> return v1 | v3;
> }
>
> +#elif RTE_BITMAP_CL_SLAB_SIZE == 16
> +static inline uint64_t
> +__rte_bitmap_line_not_empty(uint64_t *slab2)
> +{
> + uint64_t v1, v2, v3, v4, v5, v6, v7, v8;
> +
> + v1 = slab2[0] | slab2[1];
> + v2 = slab2[2] | slab2[3];
> + v3 = slab2[4] | slab2[5];
> + v4 = slab2[6] | slab2[7];
> + v5 = slab2[8] | slab2[9];
> + v6 = slab2[10] | slab2[11];
> + v7 = slab2[12] | slab2[13];
> + v8 = slab2[14] | slab2[15];
> + v1 |= v2;
> + v3 |= v4;
> + v5 |= v6;
> + v7 |= v8;
> +
> + return v1 | v3 | v5 | v7;
> +}
> +
> +#endif
> +
> /**
> * Bitmap bit clear
> *
> --
> 2.8.4
Acked-by: Cristian Dumitrescu <cristian.dumitre...@intel.com>
