From: Kiran Kumar K <kirankum...@marvell.com>
Adding support to parse 24B custom L2 header. Added devargs support to
configure the PKIND, and removed the restriction to support custom
headers on non SDP interface.
Signed-off-by: Kiran Kumar K <kirankum...@marvell.com>
---
doc/guides/nics/octeontx2.rst | 2 +-
drivers/common/octeontx2/hw/otx2_npc.h | 21 ++++++++++++++++++++-
drivers/common/octeontx2/otx2_mbox.h | 15 ++++++++++++++-
drivers/net/octeontx2/otx2_ethdev.c | 19 +++++++++++++------
drivers/net/octeontx2/otx2_ethdev_devargs.c | 8 ++++++--
drivers/net/octeontx2/otx2_rss.c | 2 +-
6 files changed, 55 insertions(+), 12 deletions(-)
diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst
index a4f224424..5e1621c1b 100644
--- a/doc/guides/nics/octeontx2.rst
+++ b/doc/guides/nics/octeontx2.rst
@@ -167,7 +167,7 @@ Runtime Config Options
With the above configuration, higig2 will be enabled on that port and the
traffic on this port should be higig2 traffic only. Supported switch header
- types are "higig2", "dsa" and "chlen90b".
+ types are "higig2", "dsa", "chlen90b" and "chlen24b".
- ``RSS tag as XOR`` (default ``0``)
diff --git a/drivers/common/octeontx2/hw/otx2_npc.h
b/drivers/common/octeontx2/hw/otx2_npc.h
index 45e60dfd5..dd507d57a 100644
--- a/drivers/common/octeontx2/hw/otx2_npc.h
+++ b/drivers/common/octeontx2/hw/otx2_npc.h
@@ -185,7 +185,11 @@ enum npc_kpu_la_ltype {
NPC_LT_LA_IH_2_ETHER,
NPC_LT_LA_HIGIG2_ETHER,
NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
- NPC_LT_LA_CH_LEN_90B_ETHER, /* Custom L2 header of length 90 bytes */
+ NPC_LT_LA_CUSTOM_L2_90B_ETHER,
+ NPC_LT_LA_CPT_HDR,
+ NPC_LT_LA_CUSTOM_L2_24B_ETHER,
+ NPC_LT_LA_CUSTOM0 = 0xE,
+ NPC_LT_LA_CUSTOM1 = 0xF,
};
enum npc_kpu_lb_ltype {
@@ -200,6 +204,9 @@ enum npc_kpu_lb_ltype {
NPC_LT_LB_EDSA_VLAN,
NPC_LT_LB_EXDSA,
NPC_LT_LB_EXDSA_VLAN,
+ NPC_LT_LB_FDSA,
+ NPC_LT_LB_CUSTOM0 = 0xE,
+ NPC_LT_LB_CUSTOM1 = 0xF,
};
enum npc_kpu_lc_ltype {
@@ -213,6 +220,8 @@ enum npc_kpu_lc_ltype {
NPC_LT_LC_MPLS,
NPC_LT_LC_NSH,
NPC_LT_LC_FCOE,
+ NPC_LT_LC_CUSTOM0 = 0xE,
+ NPC_LT_LC_CUSTOM1 = 0xF,
};
/* Don't modify Ltypes up to SCTP, otherwise it will
@@ -224,6 +233,8 @@ enum npc_kpu_ld_ltype {
NPC_LT_LD_ICMP,
NPC_LT_LD_SCTP,
NPC_LT_LD_ICMP6,
+ NPC_LT_LD_CUSTOM0,
+ NPC_LT_LD_CUSTOM1,
NPC_LT_LD_IGMP = 8,
NPC_LT_LD_AH,
NPC_LT_LD_GRE,
@@ -244,6 +255,8 @@ enum npc_kpu_le_ltype {
NPC_LT_LE_TU_MPLS_IN_GRE,
NPC_LT_LE_TU_NSH_IN_GRE,
NPC_LT_LE_TU_MPLS_IN_UDP,
+ NPC_LT_LE_CUSTOM0 = 0xE,
+ NPC_LT_LE_CUSTOM1 = 0xF,
};
enum npc_kpu_lf_ltype {
@@ -253,6 +266,8 @@ enum npc_kpu_lf_ltype {
NPC_LT_LF_TU_NSH_IN_VXLANGPE,
NPC_LT_LF_TU_MPLS_IN_NSH,
NPC_LT_LF_TU_3RD_NSH,
+ NPC_LT_LF_CUSTOM0 = 0xE,
+ NPC_LT_LF_CUSTOM1 = 0xF,
};
enum npc_kpu_lg_ltype {
@@ -260,6 +275,8 @@ enum npc_kpu_lg_ltype {
NPC_LT_LG_TU_IP6,
NPC_LT_LG_TU_ARP,
NPC_LT_LG_TU_ETHER_IN_NSH,
+ NPC_LT_LG_CUSTOM0 = 0xE,
+ NPC_LT_LG_CUSTOM1 = 0xF,
};
/* Don't modify Ltypes up to SCTP, otherwise it will
@@ -274,6 +291,8 @@ enum npc_kpu_lh_ltype {
NPC_LT_LH_TU_IGMP = 8,
NPC_LT_LH_TU_ESP,
NPC_LT_LH_TU_AH,
+ NPC_LT_LH_CUSTOM0 = 0xE,
+ NPC_LT_LH_CUSTOM1 = 0xF,
};
/* Structures definitions */
diff --git a/drivers/common/octeontx2/otx2_mbox.h
b/drivers/common/octeontx2/otx2_mbox.h
index f6d884c19..7e7667bf0 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -353,13 +353,26 @@ struct ready_msg_rsp {
uint16_t __otx2_io rclk_freq; /* RCLK frequency */
};
+enum npc_pkind_type {
+ NPC_RX_CHLEN24B_PKIND = 57ULL,
+ NPC_RX_CPT_HDR_PKIND,
+ NPC_RX_CHLEN90B_PKIND,
+ NPC_TX_HIGIG_PKIND,
+ NPC_RX_HIGIG_PKIND,
+ NPC_RX_EDSA_PKIND,
+ NPC_TX_DEF_PKIND,
+};
+
+#define OTX2_PRIV_FLAGS_CH_LEN_90B 254
+#define OTX2_PRIV_FLAGS_CH_LEN_24B 255
+
/* Struct to set pkind */
struct npc_set_pkind {
struct mbox_msghdr hdr;
#define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
#define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)
#define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)
-#define OTX2_PRIV_FLAGS_LEN_90B BIT_ULL(3)
+#define OTX2_PRIV_FLAGS_FDSA BIT_ULL(3)
#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
uint64_t __otx2_io mode;
#define PKIND_TX BIT_ULL(0)
diff --git a/drivers/net/octeontx2/otx2_ethdev.c
b/drivers/net/octeontx2/otx2_ethdev.c
index 6cebbe677..9bfe95d6b 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -112,15 +112,18 @@ nix_lf_switch_header_type_enable(struct otx2_eth_dev
*dev, bool enable)
if (dev->npc_flow.switch_header_type == 0)
return 0;
- if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B &&
- !otx2_dev_is_sdp(dev)) {
- otx2_err("chlen90b is not supported on non-SDP device");
- return -EINVAL;
- }
-
/* Notify AF about higig2 config */
req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
req->mode = dev->npc_flow.switch_header_type;
+ if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B) {
+ req->mode = OTX2_PRIV_FLAGS_CUSTOM;
+ req->pkind = NPC_RX_CHLEN90B_PKIND;
+ } else if (dev->npc_flow.switch_header_type ==
+ OTX2_PRIV_FLAGS_CH_LEN_24B) {
+ req->mode = OTX2_PRIV_FLAGS_CUSTOM;
+ req->pkind = NPC_RX_CHLEN24B_PKIND;
+ }
+
if (enable == 0)
req->mode = OTX2_PRIV_FLAGS_DEFAULT;
req->dir = PKIND_RX;
@@ -129,6 +132,10 @@ nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev,
bool enable)
return rc;
req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
req->mode = dev->npc_flow.switch_header_type;
+ if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B ||
+ dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_24B)
+ req->mode = OTX2_PRIV_FLAGS_DEFAULT;
+
if (enable == 0)
req->mode = OTX2_PRIV_FLAGS_DEFAULT;
req->dir = PKIND_TX;
diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c
b/drivers/net/octeontx2/otx2_ethdev_devargs.c
index d4a85bf55..71d3e9747 100644
--- a/drivers/net/octeontx2/otx2_ethdev_devargs.c
+++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c
@@ -114,7 +114,11 @@ parse_switch_header_type(const char *key, const char
*value, void *extra_args)
*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;
if (strcmp(value, "chlen90b") == 0)
- *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_LEN_90B;
+ *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_90B;
+
+ if (strcmp(value, "chlen24b") == 0)
+ *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_24B;
+
return 0;
}
@@ -198,7 +202,7 @@ RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,
OTX2_MAX_SQB_COUNT "=<8-512>"
OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
OTX2_FLOW_MAX_PRIORITY "=<1-32>"
- OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b>"
+ OTX2_SWITCH_HEADER_TYPE
"=<higig2|dsa|chlen90b|chlen24b>"
OTX2_RSS_TAG_AS_XOR "=1"
OTX2_NPA_LOCK_MASK "=<1-65535>"
OTX2_LOCK_RX_CTX "=1"
diff --git a/drivers/net/octeontx2/otx2_rss.c b/drivers/net/octeontx2/otx2_rss.c
index 3ba2366b8..7dbe5f69a 100644
--- a/drivers/net/octeontx2/otx2_rss.c
+++ b/drivers/net/octeontx2/otx2_rss.c
@@ -234,7 +234,7 @@ otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev, uint64_t
ethdev_rss,
dev->rss_info.nix_rss = ethdev_rss;
if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
- dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B) {
+ dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B) {
flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
}
--
2.25.1
