https://bugs.dpdk.org/show_bug.cgi?id=596
Bug ID: 596
Summary: TSO does not support split segment with TIMESTAMP
option in the header (Intel Corporation 82599ES
10-Gigabit)
Product: DPDK
Version: 20.08
Hardware: x86
OS: Linux
Status: UNCONFIRMED
Severity: normal
Priority: Normal
Component: ethdev
Assignee: dev@dpdk.org
Reporter: liu.lance...@gmail.com
Target Milestone: ---
I try to enable TIMESTAMP option on my userspace tcp stack, and enabled TSO
offloading feature, But the problems is that the ixgbe driver not split segment
right.
Send: ETHER_HEADER(14bytes) + IP_HEADER (20bytes) + TCP_HEADER(20bytes)+
TCP_HEADER_OPT (12 bytes) + payload (6400 bytes)
TCP_HEADER_OPT : TCP_OPT_NOP(1 byte) + TCP_OPT_NOP(1 byte) + TCP_OPT_TIMESTAMP
(1 byte) + TCP_OPT_TIMESTAMP_LEN (1 byte, value is 10) + ts[0](4 bytes, value
is 0) + ts[1] (4 bytes, value is 0)
m_buf->tso_size = 1460
rightly, it should split this packet to packet[0] (seq -> seq+1459) + packet[1]
(seq + 1460 -> seq + 2919) + packet[2] (seq + 2920 -> seq + 4379) + packet[3]
(seq + 4380, seq + 5839) + packet[4] (seq + 5840, seq + 6400)
But on the receive side, can only receive 1 packet about this segment (and it
is the last segment)
the NIC is as follows:
31:00.0 Ethernet controller: Intel Corporation 82599ES 10-Gigabit SFI/SFP+
Network Connection (rev 01)
Subsystem: Gigabyte Technology Co., Ltd Device ffff
Physical Slot: 11
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 142
NUMA node: 3
Region 0: Memory at e0a00000 (64-bit, non-prefetchable) [size=2M]
Region 2: I/O ports at 3020 [size=32]
Region 4: Memory at e0c04000 (64-bit, non-prefetchable) [size=16K]
Expansion ROM at e0800000 [disabled] [size=2M]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold-)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME-
Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
Address: 0000000000000000 Data: 0000
Masking: 00000000 Pending: 00000000
Capabilities: [70] MSI-X: Enable- Count=64 Masked-
Vector table: BAR=4 offset=00000000
PBA: BAR=4 offset=00002000
Capabilities: [a0] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns,
L1 <64us
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+
SlotPowerLimit 0.000W
DevCtl: Report errors: Correctable- Non-Fatal- Fatal-
Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr-
TransPend-
LnkCap: Port #0, Speed 5GT/s, Width x8, ASPM L0s, Exit Latency
L0s unlimited, L1 <8us
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive-
BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-,
OBFF Not Supported
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-,
OBFF Disabled
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range,
EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB,
EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-,
LinkEqualizationRequest-
Capabilities: [e0] Vital Product Data
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