Hi,
> -----Original Message-----
> From: Alexander Kozyrev <akozy...@nvidia.com>
> Sent: Sunday, November 15, 2020 4:26 PM
> To: dev@dpdk.org
> Cc: sta...@dpdk.org; Raslan Darawsheh <rasl...@nvidia.com>; Dekel Peled
> <dek...@nvidia.com>; Matan Azrad <ma...@nvidia.com>
> Subject: [PATCH] net/mlx5: fix packet padding config for RxQ via DevX
>
> Received packets can be aligned to the size of the cache line on
> PCI transactions. This could improve performance by avoiding
> partial cache line writes in exchange for increased PCI bandwidth.
>
> This feature is supposed to be controlled by the rxq_pkt_pad_en
> devarg and it is true for an RxQ created via the Verbs API.
> But in the DevX API case, it is erroneously controlled by the
> rxq_cqe_pad_en devarg instead, which is in charge of the CQE
> padding instead and should not control the RxQ creation.
>
> Fix DevX RxQ creation by using the proper configuration flag for
> Rx packet padding that is being set by the rxq_pkt_pad_en devarg.
>
> Fixes: dc9ceff73c ("net/mlx5: create advanced RxQ via DevX")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Alexander Kozyrev <akozy...@nvidia.com>
> Acked-by: Matan Azrad <ma...@nvidia.com>
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
