> -----Original Message-----
> From: McDaniel, Timothy <timothy.mcdan...@intel.com>
> Sent: Friday, October 30, 2020 1:28 PM
> Cc: dev@dpdk.org; Carrillo, Erik G <erik.g.carri...@intel.com>; Eads, Gage
> <gage.e...@intel.com>; Van Haaren, Harry <harry.van.haa...@intel.com>;
> jer...@marvell.com; tho...@monjalon.net
> Subject: [PATCH v10 18/23] event/dlb: add dequeue and its burst variants
> 
> Add support for dequeue, dequeue_burst, ...
> 
> DLB does not currently support interrupts, but instead uses
> umonitor/umwait if supported by the processor. This allows
> the software to monitor and wait on writes to a cache-line.
> 
> DLB supports normal and sparse cq mode. In normal mode the
> hardware will pack 4 QEs into each cache line. In sparse cq
> mode, the hardware will only populate one QE per cache line.
> Software must be aware of the cq mode, and take the appropriate
> actions, based on the mode.
> 
> Signed-off-by: Timothy McDaniel <timothy.mcdan...@intel.com>

I believe I added my tag to the v5 of this patch, but for good measure:
Reviewed-by: Gage Eads <gage.e...@intel.com>

Thanks,
Gage

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