Change formatting so that it's more consistent and readable, add/modify
comments/stdout messages, move configuration options to more appropriate
places and make the order consistent according to these rules:
1. First list generic configuration options, then list options that may
be overwritten. List SoC-specific options last.
2. For SoC-specific options, list number of cores before the number of
NUMA nodes, to make it consistent with config/meson.build.
Signed-off-by: Juraj Linkeš <juraj.lin...@pantheon.tech>
---
config/arm/meson.build | 84 +++++++++++++++++++++++++-----------------
1 file changed, 51 insertions(+), 33 deletions(-)
diff --git a/config/arm/meson.build b/config/arm/meson.build
index bd2acfc21..c970c8803 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -5,6 +5,7 @@
arm_force_native_march = false
+# common flags to all aarch64 builds, with lowest priority
flags_common_default = [
# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
# to determine the best threshold in code. Refer to notes in source file
@@ -12,8 +13,8 @@ flags_common_default = [
['RTE_ARCH_ARM64_MEMCPY', false],
# ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
# ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
- # Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless
there're
- # strong reasons.
+ # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
+ # unless there are strong reasons.
# ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
# ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
# ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
@@ -24,65 +25,82 @@ flags_common_default = [
['RTE_SCHED_VECTOR', false],
['RTE_ARM_USE_WFE', false],
+ ['RTE_ARCH_ARM64', true],
+ ['RTE_CACHE_LINE_SIZE', 128]
]
+# implementer specific generic aarch64 flags, with middle priority
+# (will overwrite common flags)
flags_generic = [
['RTE_MACHINE', '"armv8a"'],
- ['RTE_MAX_LCORE', 256],
['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_CACHE_LINE_SIZE', 128]]
+ ['RTE_CACHE_LINE_SIZE', 128],
+ ['RTE_MAX_LCORE', 256]
+]
flags_arm = [
['RTE_MACHINE', '"armv8a"'],
- ['RTE_MAX_LCORE', 16],
['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_CACHE_LINE_SIZE', 64]]
+ ['RTE_CACHE_LINE_SIZE', 64],
+ ['RTE_MAX_LCORE', 16]
+]
flags_cavium = [
+ ['RTE_MAX_VFIO_GROUPS', 128],
['RTE_CACHE_LINE_SIZE', 128],
- ['RTE_MAX_NUMA_NODES', 2],
['RTE_MAX_LCORE', 96],
- ['RTE_MAX_VFIO_GROUPS', 128]]
+ ['RTE_MAX_NUMA_NODES', 2]
+]
flags_dpaa = [
['RTE_MACHINE', '"dpaa"'],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
['RTE_USE_C11_MEM_MODEL', true],
['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_NUMA_NODES', 1],
['RTE_MAX_LCORE', 16],
- ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+ ['RTE_MAX_NUMA_NODES', 1]
+]
flags_emag = [
['RTE_MACHINE', '"emag"'],
['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_NUMA_NODES', 1],
- ['RTE_MAX_LCORE', 32]]
+ ['RTE_MAX_LCORE', 32],
+ ['RTE_MAX_NUMA_NODES', 1]
+]
flags_armada = [
['RTE_MACHINE', '"armv8a"'],
['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_NUMA_NODES', 1],
- ['RTE_MAX_LCORE', 16]]
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+]
+# part number specific aarch64 flags, with highest priority
+# (will overwrite both common and implementer specific flags)
flags_n1sdp_extra = [
['RTE_MACHINE', '"n1sdp"'],
- ['RTE_MAX_NUMA_NODES', 1],
- ['RTE_MAX_LCORE', 4],
['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
- ['RTE_LIBRTE_VHOST_NUMA', false]]
+ ['RTE_LIBRTE_VHOST_NUMA', false],
+ ['RTE_MAX_LCORE', 4],
+ ['RTE_MAX_NUMA_NODES', 1]
+]
flags_thunderx_extra = [
['RTE_MACHINE', '"thunderx"'],
- ['RTE_USE_C11_MEM_MODEL', false]]
+ ['RTE_USE_C11_MEM_MODEL', false]
+]
flags_thunderx2_extra = [
['RTE_MACHINE', '"thunderx2"'],
+ ['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_USE_C11_MEM_MODEL', true],
['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_NUMA_NODES', 2],
['RTE_MAX_LCORE', 256],
- ['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_USE_C11_MEM_MODEL', true]]
+ ['RTE_MAX_NUMA_NODES', 2]
+]
flags_octeontx2_extra = [
['RTE_MACHINE', '"octeontx2"'],
- ['RTE_MAX_NUMA_NODES', 1],
- ['RTE_MAX_LCORE', 36],
['RTE_ARM_FEATURE_ATOMICS', true],
+ ['RTE_USE_C11_MEM_MODEL', true],
['RTE_EAL_IGB_UIO', false],
- ['RTE_USE_C11_MEM_MODEL', true]]
+ ['RTE_MAX_LCORE', 36],
+ ['RTE_MAX_NUMA_NODES', 1]
+]
+# arm config (implementer 0x41) is the default config
part_number_config_default = [
['generic', ['-march=armv8-a+crc', '-moutline-atomics']],
['native', ['-march=native']],
@@ -93,8 +111,8 @@ part_number_config_default = [
['0xd09', ['-mcpu=cortex-a73']],
['0xd0a', ['-mcpu=cortex-a75']],
['0xd0b', ['-mcpu=cortex-a76']],
- ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'],
flags_n1sdp_extra]]
-
+ ['0xd0c', ['-march=armv8.2-a+crc+crypto', '-mcpu=neoverse-n1'],
flags_n1sdp_extra]
+]
part_number_config_cavium = [
['generic', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
['native', ['-march=native']],
@@ -102,11 +120,12 @@ part_number_config_cavium = [
['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra],
['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'],
flags_thunderx2_extra],
- ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'],
flags_octeontx2_extra]]
-
+ ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'],
flags_octeontx2_extra]
+]
part_number_config_emag = [
['generic', ['-march=armv8-a+crc+crypto', '-mtune=emag']],
- ['native', ['-march=native']]]
+ ['native', ['-march=native']]
+]
## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
implementer_generic = ['Generic armv8', flags_generic,
part_number_config_default]
@@ -128,15 +147,14 @@ dpdk_conf.set('RTE_ARCH_ARM', 1)
dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
if dpdk_conf.get('RTE_ARCH_32')
+ # armv7 build
dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
dpdk_conf.set('RTE_ARCH_ARMv7', 1)
# the minimum architecture supported, armv7-a, needs the following,
# mk/machine/armv7a/rte.vars.mk sets it too
machine_args += '-mfpu=neon'
else
- dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
- dpdk_conf.set('RTE_ARCH_ARM64', 1)
-
+ # aarch64 build
implementer_id = 'generic'
machine_args = [] # Clear previous machine args
if machine == 'generic' and not meson.is_cross_build()
@@ -199,7 +217,7 @@ else
endif
endforeach
endif
-message(machine_args)
+message('Using machine args: @0@'.format(machine_args))
if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
cc.get_define('__aarch64__', args: machine_args) != '')
--
2.20.1
