From: Jay Ding <jay.d...@broadcom.com>
Add SR support in truflow.
Signed-off-by: Jay Ding <jay.d...@broadcom.com>
Reviewed-by: Farah Smith <farah.sm...@broadcom.com>
---
drivers/net/bnxt/tf_core/cfa_resource_types.h | 95 ++++++++++-----------------
drivers/net/bnxt/tf_core/tf_core.c | 3 +-
drivers/net/bnxt/tf_core/tf_device.c | 9 ++-
drivers/net/bnxt/tf_core/tf_device_p4.c | 25 ++++++-
drivers/net/bnxt/tf_core/tf_device_p4.h | 6 ++
drivers/net/bnxt/tf_core/tf_device_p45.h | 89 +++++++++++++++++++++++++
6 files changed, 161 insertions(+), 66 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h
b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index 19838c3..a62063b 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -1,6 +1,13 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2020 Broadcom
- * All rights reserved.
+/*
+ * Copyright(c) 2001-2020, Broadcom. All rights reserved. The
+ * term Broadcom refers to Broadcom Inc. and/or its subsidiaries.
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * DO NOT MODIFY!!! This file is automatically generated.
*/
#ifndef _CFA_RESOURCE_TYPES_H_
@@ -64,79 +71,47 @@
#define CFA_RESOURCE_TYPE_P59_LAST CFA_RESOURCE_TYPE_P59_VEB_TCAM
-/* Multicast Group */
-#define CFA_RESOURCE_TYPE_P58_MCG 0x0UL
-/* Encap 8 byte record */
-#define CFA_RESOURCE_TYPE_P58_ENCAP_8B 0x1UL
-/* Encap 16 byte record */
-#define CFA_RESOURCE_TYPE_P58_ENCAP_16B 0x2UL
-/* Encap 64 byte record */
-#define CFA_RESOURCE_TYPE_P58_ENCAP_64B 0x3UL
-/* Source Property MAC */
-#define CFA_RESOURCE_TYPE_P58_SP_MAC 0x4UL
-/* Source Property MAC and IPv4 */
-#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV4 0x5UL
-/* Source Property MAC and IPv6 */
-#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV6 0x6UL
-/* Network Address Translation Port */
-#define CFA_RESOURCE_TYPE_P58_NAT_PORT 0x7UL
-/* Network Address Translation IPv4 address */
-#define CFA_RESOURCE_TYPE_P58_NAT_IPV4 0x8UL
/* Meter */
-#define CFA_RESOURCE_TYPE_P58_METER 0x9UL
-/* Flow State */
-#define CFA_RESOURCE_TYPE_P58_FLOW_STATE 0xaUL
-/* Full Action Records */
-#define CFA_RESOURCE_TYPE_P58_FULL_ACTION 0xbUL
-/* Action Record Format 0 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_0_ACTION 0xcUL
-/* Action Record Ext Format 0 */
-#define CFA_RESOURCE_TYPE_P58_EXT_FORMAT_0_ACTION 0xdUL
-/* Action Record Format 1 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_1_ACTION 0xeUL
-/* Action Record Format 2 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_2_ACTION 0xfUL
-/* Action Record Format 3 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_3_ACTION 0x10UL
-/* Action Record Format 4 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_4_ACTION 0x11UL
-/* Action Record Format 5 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_5_ACTION 0x12UL
-/* Action Record Format 6 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_6_ACTION 0x13UL
+#define CFA_RESOURCE_TYPE_P58_METER 0x0UL
+/* SRAM_Bank_0 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_0 0x1UL
+/* SRAM_Bank_1 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_1 0x2UL
+/* SRAM_Bank_2 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_2 0x3UL
+/* SRAM_Bank_3 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 0x4UL
/* L2 Context TCAM High priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH 0x14UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH 0x5UL
/* L2 Context TCAM Low priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW 0x15UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW 0x6UL
/* L2 Context REMAP high priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH 0x16UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH 0x7UL
/* L2 Context REMAP Low priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW 0x17UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW 0x8UL
/* Profile Func */
-#define CFA_RESOURCE_TYPE_P58_PROF_FUNC 0x18UL
+#define CFA_RESOURCE_TYPE_P58_PROF_FUNC 0x9UL
/* Profile TCAM */
-#define CFA_RESOURCE_TYPE_P58_PROF_TCAM 0x19UL
+#define CFA_RESOURCE_TYPE_P58_PROF_TCAM 0xaUL
/* Exact Match Profile Id */
-#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID 0x1aUL
+#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID 0xbUL
/* Wildcard Profile Id */
-#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID 0x1bUL
+#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID 0xcUL
/* Exact Match Record */
-#define CFA_RESOURCE_TYPE_P58_EM_REC 0x1cUL
+#define CFA_RESOURCE_TYPE_P58_EM_REC 0xdUL
/* Wildcard TCAM */
-#define CFA_RESOURCE_TYPE_P58_WC_TCAM 0x1dUL
+#define CFA_RESOURCE_TYPE_P58_WC_TCAM 0xeUL
/* Meter profile */
-#define CFA_RESOURCE_TYPE_P58_METER_PROF 0x1eUL
+#define CFA_RESOURCE_TYPE_P58_METER_PROF 0xfUL
/* Meter */
-#define CFA_RESOURCE_TYPE_P58_MIRROR 0x1fUL
-/* Source Property TCAM */
-#define CFA_RESOURCE_TYPE_P58_SP_TCAM 0x20UL
+#define CFA_RESOURCE_TYPE_P58_MIRROR 0x10UL
/* Exact Match Flexible Key Builder */
-#define CFA_RESOURCE_TYPE_P58_EM_FKB 0x21UL
+#define CFA_RESOURCE_TYPE_P58_EM_FKB 0x11UL
/* Wildcard Flexible Key Builder */
-#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x22UL
+#define CFA_RESOURCE_TYPE_P58_WC_FKB 0x12UL
/* VEB TCAM */
-#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x23UL
-#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_VEB_TCAM
+#define CFA_RESOURCE_TYPE_P58_VEB_TCAM 0x13UL
+#define CFA_RESOURCE_TYPE_P58_LAST CFA_RESOURCE_TYPE_P58_VEB_TCAM
/* Multicast Group */
diff --git a/drivers/net/bnxt/tf_core/tf_core.c
b/drivers/net/bnxt/tf_core/tf_core.c
index 0dbde1d..788335b 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -34,7 +34,8 @@ tf_open_session(struct tf *tfp,
* side. It is assumed that the Firmware will be supported if
* firmware open session succeeds.
*/
- if (parms->device_type != TF_DEVICE_TYPE_WH) {
+ if (parms->device_type != TF_DEVICE_TYPE_WH &&
+ parms->device_type != TF_DEVICE_TYPE_SR) {
TFP_DRV_LOG(ERR,
"Unsupported device type %d\n",
parms->device_type);
diff --git a/drivers/net/bnxt/tf_core/tf_device.c
b/drivers/net/bnxt/tf_core/tf_device.c
index 1129440..8389828 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -47,7 +47,6 @@ tf_dev_bind_p4(struct tf *tfp,
struct tf_if_tbl_cfg_parms if_tbl_cfg;
struct tf_global_cfg_cfg_parms global_cfg;
- dev_handle->type = TF_DEVICE_TYPE_WH;
/* Initial function initialization */
dev_handle->ops = &tf_dev_ops_p4_init;
@@ -90,7 +89,10 @@ tf_dev_bind_p4(struct tf *tfp,
* EEM
*/
em_cfg.num_elements = TF_EM_TBL_TYPE_MAX;
- em_cfg.cfg = tf_em_ext_p4;
+ if (dev_handle->type == TF_DEVICE_TYPE_WH)
+ em_cfg.cfg = tf_em_ext_p4;
+ else
+ em_cfg.cfg = tf_em_ext_p45;
em_cfg.resources = resources;
em_cfg.mem_type = TF_EEM_MEM_TYPE_HOST;
rc = tf_em_ext_common_bind(tfp, &em_cfg);
@@ -241,6 +243,8 @@ tf_dev_bind(struct tf *tfp __rte_unused,
{
switch (type) {
case TF_DEVICE_TYPE_WH:
+ case TF_DEVICE_TYPE_SR:
+ dev_handle->type = type;
return tf_dev_bind_p4(tfp,
shadow_copy,
resources,
@@ -258,6 +262,7 @@ tf_dev_unbind(struct tf *tfp,
{
switch (dev_handle->type) {
case TF_DEVICE_TYPE_WH:
+ case TF_DEVICE_TYPE_SR:
return tf_dev_unbind_p4(tfp);
default:
TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c
b/drivers/net/bnxt/tf_core/tf_device_p4.c
index fe8dec3..0344565 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -28,13 +28,32 @@
* - (-EINVAL) on failure.
*/
static int
-tf_dev_p4_get_max_types(struct tf *tfp __rte_unused,
+tf_dev_p4_get_max_types(struct tf *tfp,
uint16_t *max_types)
{
- if (max_types == NULL)
+ struct tf_session *tfs;
+ struct tf_dev_info *dev;
+ int rc;
+
+ if (max_types == NULL || tfp == NULL)
return -EINVAL;
- *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;
+ /* Retrieve the session information */
+ rc = tf_session_get_session(tfp, &tfs);
+ if (rc)
+ return rc;
+
+ /* Retrieve the device information */
+ rc = tf_session_get_device(tfs, &dev);
+ if (rc)
+ return rc;
+
+ if (dev->type == TF_DEVICE_TYPE_WH)
+ *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;
+ else if (dev->type == TF_DEVICE_TYPE_SR)
+ *max_types = CFA_RESOURCE_TYPE_P45_LAST + 1;
+ else
+ return -ENODEV;
return 0;
}
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h
b/drivers/net/bnxt/tf_core/tf_device_p4.h
index 7e58469..aba28fe 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -83,6 +83,12 @@ struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE },
};
+struct tf_rm_element_cfg tf_em_ext_p45[TF_EM_TBL_TYPE_MAX] = {
+ /* CFA_RESOURCE_TYPE_P4_EM_REC */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
+};
+
struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC },
/* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */
diff --git a/drivers/net/bnxt/tf_core/tf_device_p45.h
b/drivers/net/bnxt/tf_core/tf_device_p45.h
index 2da59d1..016d6e2 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p45.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p45.h
@@ -13,4 +13,93 @@
#include "tf_if_tbl.h"
#include "tf_global_cfg.h"
+struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_FUNC },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM_PROF_ID },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_EM_PROF_ID },
+ /* CFA_RESOURCE_TYPE_P45_L2_FUNC */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+};
+
+struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_TCAM },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_TCAM },
+ /* CFA_RESOURCE_TYPE_P45_CT_RULE_TCAM */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_VEB_TCAM */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+};
+
+struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_FULL_ACTION },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MCG },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_8B },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_16B },
+ /* CFA_RESOURCE_TYPE_P45_ENCAP_32B */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_64B },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV4 },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_COUNTER_64B },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_IPV4 },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER_PROF },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MIRROR },
+ /* CFA_RESOURCE_TYPE_P45_UPAR */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_EPOC */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_METADATA */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_CT_STATE */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_RANGE_PROF */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_RANGE_ENTRY */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_LAG */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_VNIC_SVIF */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_EM_FBK */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_WC_FKB */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ /* CFA_RESOURCE_TYPE_P45_EXT */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+};
+
+struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
+ /* CFA_RESOURCE_TYPE_P45_EM_REC */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+ { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
+};
+
+struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
+ { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P45_EM_REC },
+ /* CFA_RESOURCE_TYPE_P45_TBL_SCOPE */
+ { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+};
+
+struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {
+ { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },
+ { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },
+ { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },
+ { TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },
+ { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },
+ { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }
+};
+
+struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {
+ { TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },
+ { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },
+};
#endif /* _TF_DEVICE_P45_H_ */
--
2.7.4
