On 09-Oct-20 5:09 PM, Jerin Jacob wrote:
On Fri, Oct 9, 2020 at 9:32 PM Anatoly Burakov
<anatoly.bura...@intel.com> wrote:
From: Liang Ma <liang.j...@intel.com>
Add two new power management intrinsics, and provide an implementation
in eal/x86 based on UMONITOR/UMWAIT instructions. The instructions
are implemented as raw byte opcodes because there is not yet widespread
compiler support for these instructions.
The power management instructions provide an architecture-specific
function to either wait until a specified TSC timestamp is reached, or
optionally wait until either a TSC timestamp is reached or a memory
location is written to. The monitor function also provides an optional
comparison, to avoid sleeping when the expected write has already
happened, and no more writes are expected.
For more details, please refer to Intel(R) 64 and IA-32 Architectures
Software Developer's Manual, Volume 2.
Signed-off-by: Liang Ma <liang.j...@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.bura...@intel.com>
---
Notes:
v5:
- Removed return values
- Simplified intrinsics and hardcoded C0.2 state
- Added other arch stubs
<snip>
+
+/**
+ * This function is not supported on ARM.
+ *
+ * @param p
+ * Address to monitor for changes. Must be aligned on an 64-byte boundary.
+ * @param expected_value
+ * Before attempting the monitoring, the `p` address may be read and compared
+ * against this value. If `value_mask` is zero, this step will be skipped.
+ * @param value_mask
+ * The 64-bit mask to use to extract current value from `p`.
+ * @param tsc_timestamp
+ * Maximum TSC timestamp to wait for.
+ *
+ * @return
+ * - 0 on success
remove return as it is a void function
Oops, will fix in v6. Thanks!
--
Thanks,
Anatoly
