> -----Original Message-----
> From: Power, Ciara <ciara.po...@intel.com>
> Sent: Wednesday, September 30, 2020 9:04 PM
> To: dev@dpdk.org
> Cc: Power, Ciara <ciara.po...@intel.com>; Yang, Qiming
> <qiming.y...@intel.com>; Zhang, Qi Z <qi.z.zh...@intel.com>
> Subject: [PATCH v3 10/18] net/ice: add checks for max SIMD bitwidth
>
> When choosing a vector path to take, an extra condition must be satisfied to
> ensure the max SIMD bitwidth allows for the CPU enabled path.
>
> Cc: Qiming Yang <qiming.y...@intel.com>
> Cc: Qi Zhang <qi.z.zh...@intel.com>
>
> Signed-off-by: Ciara Power <ciara.po...@intel.com>
Acked-by: Qi Zhang <qi.z.zh...@intel.com>
> ---
> drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index
> fef6ad4544..5a29af743c 100644
> --- a/drivers/net/ice/ice_rxtx.c
> +++ b/drivers/net/ice/ice_rxtx.c
> @@ -2936,7 +2936,9 @@ ice_set_rx_function(struct rte_eth_dev *dev)
> bool use_avx2 = false;
>
> if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
> - if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
> + if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed &&
> + rte_get_max_simd_bitwidth()
> + >= RTE_MAX_128_SIMD) {
> ad->rx_vec_allowed = true;
> for (i = 0; i < dev->data->nb_rx_queues; i++) {
> rxq = dev->data->rx_queues[i];
> @@ -2946,8 +2948,10 @@ ice_set_rx_function(struct rte_eth_dev *dev)
> }
> }
>
> - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
> - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
> + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
> + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
> + rte_get_max_simd_bitwidth()
> + >= RTE_MAX_256_SIMD)
> use_avx2 = true;
>
> } else {
> @@ -3114,7 +3118,9 @@ ice_set_tx_function(struct rte_eth_dev *dev)
> bool use_avx2 = false;
>
> if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
> - if (!ice_tx_vec_dev_check(dev)) {
> + if (!ice_tx_vec_dev_check(dev) &&
> + rte_get_max_simd_bitwidth()
> + >= RTE_MAX_128_SIMD) {
> ad->tx_vec_allowed = true;
> for (i = 0; i < dev->data->nb_tx_queues; i++) {
> txq = dev->data->tx_queues[i];
> @@ -3124,8 +3130,10 @@ ice_set_tx_function(struct rte_eth_dev *dev)
> }
> }
>
> - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
> - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
> + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
> + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
> + rte_get_max_simd_bitwidth()
> + >= RTE_MAX_256_SIMD)
> use_avx2 = true;
>
> } else {
> --
> 2.17.1
