> diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
> new file mode 100644
> index 0000000..7ff7dac
> --- /dev/null
> +++ b/drivers/event/dlb2/dlb2.c
> @@ -0,0 +1,557 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2016-2020 Intel Corporation
> + */
> +
> +#include <assert.h>
> +#include <errno.h>
> +#include <nmmintrin.h>
> +#include <pthread.h>
> +#include <stdint.h>
> +#include <stdbool.h>
> +#include <stdio.h>
> +#include <string.h>
> +#include <sys/mman.h>
> +#include <sys/fcntl.h>
> +
> +#include <rte_common.h>
> +#include <rte_config.h>
> +#include <rte_cycles.h>
> +#include <rte_debug.h>
> +#include <rte_dev.h>
> +#include <rte_errno.h>
> +#include <rte_eventdev.h>
> +#include <rte_eventdev_pmd.h>
> +#include <rte_kvargs.h>
> +#include <rte_io.h>
Nit: flip the order of rte_kvargs.h and rte_io.h
> +#include <rte_log.h>
> +#include <rte_malloc.h>
> +#include <rte_mbuf.h>
> +#include <rte_prefetch.h>
> +#include <rte_ring.h>
> +#include <rte_string_fns.h>
> +
> +#include "dlb2_priv.h"
> +#include "dlb2_iface.h"
> +#include "dlb2_inline_fns.h"
> +
> +#if !defined RTE_ARCH_X86_64
> +#error "This implementation only supports RTE_ARCH_X86_64 architecture."
> +#endif
In patch #1, meson.build allows RTE_ARCH_X86 -- should that be removed?
> +
> +/*
> + * Resources exposed to eventdev. Some values overridden at runtime using
> + * values returned by the DLB kernel driver.
> + */
> +#if (RTE_EVENT_MAX_QUEUES_PER_DEV > UINT8_MAX)
> +#error "RTE_EVENT_MAX_QUEUES_PER_DEV cannot fit in member
> max_event_queues"
> +#endif
> +static struct rte_event_dev_info evdev_dlb2_default_info = {
> + .driver_name = "", /* probe will set */
> + .min_dequeue_timeout_ns = DLB2_MIN_DEQUEUE_TIMEOUT_NS,
> + .max_dequeue_timeout_ns = DLB2_MAX_DEQUEUE_TIMEOUT_NS,
> +#if (RTE_EVENT_MAX_QUEUES_PER_DEV < DLB2_MAX_NUM_LDB_QUEUES)
> + .max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV,
> +#else
> + .max_event_queues = DLB2_MAX_NUM_LDB_QUEUES,
> +#endif
> + .max_event_queue_flows = DLB2_MAX_NUM_FLOWS,
> + .max_event_queue_priority_levels = DLB2_QID_PRIORITIES,
> + .max_event_priority_levels = DLB2_QID_PRIORITIES,
> + .max_event_ports = DLB2_MAX_NUM_LDB_PORTS,
> + .max_event_port_dequeue_depth = DLB2_MAX_CQ_DEPTH,
> + .max_event_port_enqueue_depth = DLB2_MAX_ENQUEUE_DEPTH,
> + .max_event_port_links = DLB2_MAX_NUM_QIDS_PER_LDB_CQ,
> + .max_num_events = DLB2_MAX_NUM_LDB_CREDITS,
> + .max_single_link_event_port_queue_pairs =
> DLB2_MAX_NUM_DIR_PORTS,
> + .event_dev_cap = (RTE_EVENT_DEV_CAP_QUEUE_QOS |
> + RTE_EVENT_DEV_CAP_EVENT_QOS |
> + RTE_EVENT_DEV_CAP_BURST_MODE |
> + RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
> + RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE |
> + RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES),
> +};
> +
> +/* These functions will vary based on processor capabilities */
> +static struct dlb2_port_low_level_io_functions qm_mmio_fns;
> +
> +struct process_local_port_data
> +dlb2_port[DLB2_MAX_NUM_PORTS][DLB2_NUM_PORT_TYPES];
> +
> +/* override defaults with value(s) provided on command line */
> +static void
> +dlb2_init_queue_depth_thresholds(struct dlb2_eventdev *dlb2,
> + int *qid_depth_thresholds)
> +{
> + int q;
> +
> + for (q = 0; q < DLB2_MAX_NUM_QUEUES; q++) {
> + if (qid_depth_thresholds[q] != 0)
> + dlb2->ev_queues[q].depth_threshold =
> + qid_depth_thresholds[q];
> + }
> +}
> +
> +static int
> +dlb2_hw_query_resources(struct dlb2_eventdev *dlb2)
> +{
> + struct dlb2_hw_dev *handle = &dlb2->qm_instance;
> + struct dlb2_hw_resource_info *dlb2_info = &handle->info;
> + int ret;
> +
> + /* Query driver resources provisioned for this VF */
"VF" -> "device"?
> +
> + ret = dlb2_iface_get_num_resources(handle,
> + &dlb2->hw_rsrc_query_results);
> + if (ret) {
> + DLB2_LOG_ERR("ioctl get dlb2 num resources, err=%d\n",
> + ret);
Nit: this could be a one-liner
> + return ret;
> + }
> +
> + /* Complete filling in device resource info returned to evdev app,
> + * overriding any default values.
> + * The capabilities (CAPs) were set at compile time.
> + */
> +
> + evdev_dlb2_default_info.max_event_queues =
> + dlb2->hw_rsrc_query_results.num_ldb_queues;
> +
> + evdev_dlb2_default_info.max_event_ports =
> + dlb2->hw_rsrc_query_results.num_ldb_ports;
> +
> + evdev_dlb2_default_info.max_num_events =
> + dlb2->hw_rsrc_query_results.num_ldb_credits;
> +
> + /* Save off values used when creating the scheduling domain. */
> +
> + handle->info.num_sched_domains =
> + dlb2->hw_rsrc_query_results.num_sched_domains;
> +
> + handle->info.hw_rsrc_max.nb_events_limit =
> + dlb2->hw_rsrc_query_results.num_ldb_credits;
> +
> + handle->info.hw_rsrc_max.num_queues =
> + dlb2->hw_rsrc_query_results.num_ldb_queues +
> + dlb2->hw_rsrc_query_results.num_dir_ports;
> +
> + handle->info.hw_rsrc_max.num_ldb_queues =
> + dlb2->hw_rsrc_query_results.num_ldb_queues;
> +
> + handle->info.hw_rsrc_max.num_ldb_ports =
> + dlb2->hw_rsrc_query_results.num_ldb_ports;
> +
> + handle->info.hw_rsrc_max.num_dir_ports =
> + dlb2->hw_rsrc_query_results.num_dir_ports;
> +
> + handle->info.hw_rsrc_max.reorder_window_size =
> + dlb2->hw_rsrc_query_results.num_hist_list_entries;
> +
> + rte_memcpy(dlb2_info, &handle->info.hw_rsrc_max,
> sizeof(*dlb2_info));
> +
> + return 0;
> +}
> +
> +static void
> +dlb2_qm_mmio_fn_init(void)
> +{
> + /* Process-local function pointers for performing low level port i/o */
> +
> + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MOVDIR64B))
> + qm_mmio_fns.pp_enqueue_four = dlb2_movdir64b;
> + else
> + qm_mmio_fns.pp_enqueue_four = dlb2_movntdq;
> +}
> +
> +#define RTE_BASE_10 10
> +
> +int dlb2_string_to_int(int *result, const char *str)
> +{
> + long ret;
> +
> + if (str == NULL || result == NULL)
> + return -EINVAL;
> +
> + errno = 0;
> + ret = strtol(str, NULL, RTE_BASE_10);
> + if (errno)
> + return -errno;
Looks like strtol will return 0 if 'str' doesn't contain valid numeric
characters,
but won't set errno in this case. See the "No digits were found" case in the
man page's example at the bottom:
http://man7.org/linux/man-pages/man3/strtol.3.html
> +
> + /* long int and int may be different width for some architectures */
> + if (ret < INT_MIN || ret > INT_MAX)
> + return -EINVAL;
> +
> + *result = ret;
> + return 0;
> +}
> +
> +static int
> +set_numa_node(const char *key __rte_unused, const char *value, void
> *opaque)
> +{
> + int *socket_id = opaque;
> + int ret;
> +
> + ret = dlb2_string_to_int(socket_id, value);
> + if (ret < 0)
> + return ret;
> +
> + if (*socket_id > RTE_MAX_NUMA_NODES)
> + return -EINVAL;
> + return 0;
> +}
> +
> +static int
> +set_max_num_events(const char *key __rte_unused,
> + const char *value,
> + void *opaque)
> +{
> + int *max_num_events = opaque;
> + int ret;
> +
> + if (value == NULL || opaque == NULL) {
> + DLB2_LOG_ERR("NULL pointer\n");
> + return -EINVAL;
> + }
> +
> + ret = dlb2_string_to_int(max_num_events, value);
> + if (ret < 0)
> + return ret;
> +
> +
Nit: extra newline
> + if (*max_num_events < 0 || *max_num_events >
> + DLB2_MAX_NUM_LDB_CREDITS) {
> + DLB2_LOG_ERR("dlb2: max_num_events must be between 0 and
> %d\n",
> + DLB2_MAX_NUM_LDB_CREDITS);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int
> +set_num_dir_credits(const char *key __rte_unused,
> + const char *value,
> + void *opaque)
> +{
> + int *num_dir_credits = opaque;
> + int ret;
> +
> + if (value == NULL || opaque == NULL) {
> + DLB2_LOG_ERR("NULL pointer\n");
> + return -EINVAL;
> + }
> +
> + ret = dlb2_string_to_int(num_dir_credits, value);
> + if (ret < 0)
> + return ret;
> +
> + if (*num_dir_credits < 0 ||
> + *num_dir_credits > DLB2_MAX_NUM_DIR_CREDITS) {
> + DLB2_LOG_ERR("dlb2: num_dir_credits must be between 0 and
> %d\n",
> + DLB2_MAX_NUM_DIR_CREDITS);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int
> +set_dev_id(const char *key __rte_unused,
> + const char *value,
> + void *opaque)
> +{
> + int *dev_id = opaque;
> + int ret;
> +
> + if (value == NULL || opaque == NULL) {
> + DLB2_LOG_ERR("NULL pointer\n");
> + return -EINVAL;
> + }
> +
> + ret = dlb2_string_to_int(dev_id, value);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int
> +set_cos(const char *key __rte_unused,
> + const char *value,
> + void *opaque)
> +{
> + enum dlb2_cos *cos_id = opaque;
> + int x = 0;
> + int ret;
> +
> + if (value == NULL || opaque == NULL) {
> + DLB2_LOG_ERR("NULL pointer\n");
> + return -EINVAL;
> + }
> +
> + ret = dlb2_string_to_int(&x, value);
> + if (ret < 0)
> + return ret;
> +
> + if (x != DLB2_COS_DEFAULT && (x < DLB2_COS_0 || x > DLB2_COS_3)) {
> + DLB2_LOG_ERR("COS %d out of range, must be 0-3\n", x);
If DLB2_COS_DEFAULT (-1) is a valid value, should this printf reflect that?
> + return -EINVAL;
> + }
> +
> + *cos_id = x;
> +
> + return 0;
> +}
> +
> +
> +static int
> +set_qid_depth_thresh(const char *key __rte_unused,
> + const char *value,
> + void *opaque)
> +{
> + struct dlb2_qid_depth_thresholds *qid_thresh = opaque;
> + int first, last, thresh, i;
> +
> + if (value == NULL || opaque == NULL) {
> + DLB2_LOG_ERR("NULL pointer\n");
> + return -EINVAL;
> + }
> +
> + /* command line override may take one of the following 3 forms:
> + * qid_depth_thresh=all:<threshold_value> ... all queues
> + * qid_depth_thresh=qidA-qidB:<threshold_value> ... a range of queues
> + * qid_depth_thresh=qid:<threshold_value> ... just one queue
> + */
> + if (sscanf(value, "all:%d", &thresh) == 1) {
> + first = 0;
> + last = DLB2_MAX_NUM_QUEUES - 1;
> + } else if (sscanf(value, "%d-%d:%d", &first, &last, &thresh) == 3) {
> + /* we have everything we need */
> + } else if (sscanf(value, "%d:%d", &first, &thresh) == 2) {
> + last = first;
> + } else {
> + DLB2_LOG_ERR("Error parsing qid depth vdev arg. Should be
> all:val, qid-qid:val, or qid:val\n");
"vdev arg" -> "devarg"
> + return -EINVAL;
> + }
> +
> + if (first > last || first < 0 || last >= DLB2_MAX_NUM_QUEUES) {
> + DLB2_LOG_ERR("Error parsing qid depth vdev arg, invalid qid
> value\n");
Ditto
> + return -EINVAL;
> + }
> +
> + if (thresh < 0 || thresh > DLB2_MAX_QUEUE_DEPTH_THRESHOLD) {
> + DLB2_LOG_ERR("Error parsing qid depth vdev arg, threshold >
> %d\n",
Ditto
> + DLB2_MAX_QUEUE_DEPTH_THRESHOLD);
> + return -EINVAL;
> + }
> +
> + for (i = first; i <= last; i++)
> + qid_thresh->val[i] = thresh; /* indexed by qid */
> +
> + return 0;
> +}
> +
> +static void
> +dlb2_entry_points_init(struct rte_eventdev *dev)
> +{
> + RTE_SET_USED(dev);
> +
> + /* Eventdev PMD entry points */
> +}
> +
> +int
> +dlb2_primary_eventdev_probe(struct rte_eventdev *dev,
> + const char *name,
> + struct dlb2_devargs *dlb2_args)
> +{
> + struct dlb2_eventdev *dlb2;
> + int err, i;
> +
> + dlb2 = dev->data->dev_private;
> +
> + dlb2->event_dev = dev; /* backlink */
> +
> + evdev_dlb2_default_info.driver_name = name;
> +
> + dlb2->max_num_events_override = dlb2_args->max_num_events;
> + dlb2->num_dir_credits_override = dlb2_args-
> >num_dir_credits_override;
> + dlb2->qm_instance.device_path_id = dlb2_args->dev_id;
> + dlb2->qm_instance.cos_id = dlb2_args->cos_id;
> +
> + /* Open the interface.
> + * For vdev mode, this means open the dlb2 kernel module.
> + */
> + err = dlb2_iface_open(&dlb2->qm_instance, name);
> + if (err < 0) {
> + DLB2_LOG_ERR("could not open event hardware device,
> err=%d\n",
> + err);
> + return err;
> + }
> +
> + err = dlb2_iface_get_device_version(&dlb2->qm_instance,
> + &dlb2->revision);
> + if (err < 0) {
> + DLB2_LOG_ERR("dlb2: failed to get the device version,
> err=%d\n",
> + err);
> + return err;
> + }
> +
> + err = dlb2_hw_query_resources(dlb2);
> + if (err) {
> + DLB2_LOG_ERR("get resources err=%d for %s\n",
> + err, name);
> + return err;
> + }
> +
> + dlb2_iface_hardware_init(&dlb2->qm_instance);
> +
> + err = dlb2_iface_get_cq_poll_mode(&dlb2->qm_instance, &dlb2-
> >poll_mode);
> + if (err < 0) {
> + DLB2_LOG_ERR("dlb2: failed to get the poll mode, err=%d\n",
> + err);
> + return err;
> + }
> +
> + /* Initialize each port's token pop mode */
> + for (i = 0; i < DLB2_MAX_NUM_PORTS; i++)
> + dlb2->ev_ports[i].qm_port.token_pop_mode = AUTO_POP;
> +
> + rte_spinlock_init(&dlb2->qm_instance.resource_lock);
> +
> + dlb2_qm_mmio_fn_init();
> +
> + dlb2_iface_low_level_io_init();
> +
> + dlb2_entry_points_init(dev);
> +
> + dlb2_init_queue_depth_thresholds(dlb2,
> + dlb2_args->qid_depth_thresholds.val);
> +
> + return 0;
> +}
> +
> +int
> +dlb2_secondary_eventdev_probe(struct rte_eventdev *dev,
> + const char *name)
> +{
> + struct dlb2_eventdev *dlb2;
> + int err;
> +
> + dlb2 = dev->data->dev_private;
> +
> + evdev_dlb2_default_info.driver_name = name;
> +
> + err = dlb2_iface_open(&dlb2->qm_instance, name);
> + if (err < 0) {
> + DLB2_LOG_ERR("could not open event hardware device,
> err=%d\n",
> + err);
> + return err;
> + }
> +
> + err = dlb2_hw_query_resources(dlb2);
> + if (err) {
> + DLB2_LOG_ERR("get resources err=%d for %s\n",
> + err, name);
> + return err;
> + }
> +
> + dlb2_qm_mmio_fn_init();
> +
> + dlb2_iface_low_level_io_init();
> +
> + dlb2_entry_points_init(dev);
> +
> + return 0;
> +}
> +
> +int
> +dlb2_parse_params(const char *params,
> + const char *name,
> + struct dlb2_devargs *dlb2_args)
> +{
> + int ret = 0;
> + static const char * const args[] = { NUMA_NODE_ARG,
> + DLB2_MAX_NUM_EVENTS,
> + DLB2_NUM_DIR_CREDITS,
> + DEV_ID_ARG,
> + DLB2_QID_DEPTH_THRESH_ARG,
> + DLB2_COS_ARG,
> + NULL };
Nit: const_args entries alignment
> +
> + if (params != NULL && params[0] != '\0') {
> + struct rte_kvargs *kvlist = rte_kvargs_parse(params, args);
> +
> + if (!kvlist) {
> + RTE_LOG(INFO, PMD,
> + "Ignoring unsupported parameters when creating
> device '%s'\n",
> + name);
> + } else {
> + int ret = rte_kvargs_process(kvlist, NUMA_NODE_ARG,
> + set_numa_node,
> + &dlb2_args->socket_id);
> + if (ret != 0) {
> + DLB2_LOG_ERR("%s: Error parsing numa node
> parameter",
> + name);
> + rte_kvargs_free(kvlist);
> + return ret;
> + }
> +
> + ret = rte_kvargs_process(kvlist,
> DLB2_MAX_NUM_EVENTS,
> + set_max_num_events,
> + &dlb2_args->max_num_events);
> + if (ret != 0) {
> + DLB2_LOG_ERR("%s: Error parsing
> max_num_events parameter",
> + name);
> + rte_kvargs_free(kvlist);
> + return ret;
> + }
> +
> + ret = rte_kvargs_process(kvlist,
> + DLB2_NUM_DIR_CREDITS,
> + set_num_dir_credits,
> + &dlb2_args->num_dir_credits_override);
> + if (ret != 0) {
> + DLB2_LOG_ERR("%s: Error parsing
> num_dir_credits parameter",
> + name);
> + rte_kvargs_free(kvlist);
> + return ret;
> + }
> +
> + ret = rte_kvargs_process(kvlist, DEV_ID_ARG,
> + set_dev_id,
> + &dlb2_args->dev_id);
> + if (ret != 0) {
> + DLB2_LOG_ERR("%s: Error parsing dev_id
> parameter",
> + name);
> + rte_kvargs_free(kvlist);
> + return ret;
> + }
> +
> + ret = rte_kvargs_process(
> + kvlist,
> + DLB2_QID_DEPTH_THRESH_ARG,
> + set_qid_depth_thresh,
> + &dlb2_args->qid_depth_thresholds);
> + if (ret != 0) {
> + DLB2_LOG_ERR("%s: Error parsing
> qid_depth_thresh parameter",
> + name);
> + rte_kvargs_free(kvlist);
> + return ret;
> + }
> +
> + ret = rte_kvargs_process(kvlist, DLB2_COS_ARG,
> + set_cos,
> + &dlb2_args->cos_id);
> + if (ret != 0) {
> + DLB2_LOG_ERR("%s: Error parsing cos
> parameter",
> + name);
> + rte_kvargs_free(kvlist);
> + return ret;
> + }
> +
> + rte_kvargs_free(kvlist);
> + }
> + }
> + return ret;
> +}
> +RTE_LOG_REGISTER(eventdev_dlb2_log_level, pmd.event.dlb2, NOTICE);
> +
Nit: whitespace at the end of the file
> diff --git a/drivers/event/dlb2/dlb2_iface.c b/drivers/event/dlb2/dlb2_iface.c
> new file mode 100644
> index 0000000..fefdf78
> --- /dev/null
> +++ b/drivers/event/dlb2/dlb2_iface.c
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2016-2020 Intel Corporation
> + */
> +
> +#include <stdbool.h>
> +#include <stdint.h>
> +#include <rte_debug.h>
> +#include <rte_bus_pci.h>
> +#include <rte_log.h>
> +#include <rte_dev.h>
> +#include <rte_mbuf.h>
> +#include <rte_ring.h>
> +#include <rte_errno.h>
> +#include <rte_kvargs.h>
> +#include <rte_malloc.h>
> +#include <rte_cycles.h>
> +#include <rte_io.h>
> +#include <rte_eventdev.h>
> +#include <rte_eventdev_pmd.h>
Doesn't look stdbool.h and the rte_*.h includes are needed here -- I was able
to build
the full series with them commented out.
[...]
> diff --git a/drivers/event/dlb2/pf/base/dlb2_osdep.h
> b/drivers/event/dlb2/pf/base/dlb2_osdep.h
> new file mode 100644
> index 0000000..c8d8d5b
> --- /dev/null
> +++ b/drivers/event/dlb2/pf/base/dlb2_osdep.h
> @@ -0,0 +1,248 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2016-2020 Intel Corporation
> + */
> +
> +#ifndef __DLB2_OSDEP_H
> +#define __DLB2_OSDEP_H
> +
> +#include <string.h>
> +#include <time.h>
> +#include <unistd.h>
> +#include <pthread.h>
> +
> +#include <rte_string_fns.h>
> +#include <rte_cycles.h>
> +#include <rte_io.h>
> +#include <rte_log.h>
> +#include <rte_spinlock.h>
> +#include "../dlb2_main.h"
> +#include "dlb2_resource.h"
> +#include "../../dlb2_log.h"
> +#include "../../dlb2_user.h"
> +
> +
> +#define DLB2_PCI_REG_READ(addr) rte_read32((void *)addr)
> +#define DLB2_PCI_REG_WRITE(reg, value) rte_write32(value, (void *)reg)
> +
> +/* Read/write register 'reg' in the CSR BAR space */
> +#define DLB2_CSR_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->csr_kva + (reg)))
> +#define DLB2_CSR_RD(hw, reg) \
> + DLB2_PCI_REG_READ(DLB2_CSR_REG_ADDR((hw), (reg)))
> +#define DLB2_CSR_WR(hw, reg, value) \
> + DLB2_PCI_REG_WRITE(DLB2_CSR_REG_ADDR((hw), (reg)), (value))
> +
> +/* Read/write register 'reg' in the func BAR space */
> +#define DLB2_FUNC_REG_ADDR(a, reg) ((void *)((uintptr_t)(a)->func_kva +
> (reg)))
> +#define DLB2_FUNC_RD(hw, reg) \
> + DLB2_PCI_REG_READ(DLB2_FUNC_REG_ADDR((hw), (reg)))
> +#define DLB2_FUNC_WR(hw, reg, value) \
> + DLB2_PCI_REG_WRITE(DLB2_FUNC_REG_ADDR((hw), (reg)), (value))
> +
> +/* Map to PMDs logging interface */
> +#define DLB2_ERR(dev, fmt, args...) \
> + DLB2_LOG_ERR(fmt, ## args)
> +
> +#define DLB2_INFO(dev, fmt, args...) \
> + DLB2_LOG_INFO(fmt, ## args)
> +
> +#define DLB2_DEBUG(dev, fmt, args...) \
> + DLB2_LOG_DBG(fmt, ## args)
> +
> +/**
> + * os_udelay() - busy-wait for a number of microseconds
> + * @usecs: delay duration.
> + */
> +static inline void os_udelay(int usecs)
> +{
> + rte_delay_us(usecs);
> +}
> +
> +/**
> + * os_msleep() - sleep for a number of milliseconds
> + * @usecs: delay duration.
> + */
> +static inline void os_msleep(int msecs)
> +{
> + rte_delay_ms(msecs);
> +}
> +
> +#define DLB2_PP_BASE(__is_ldb) \
> + ((__is_ldb) ? DLB2_LDB_PP_BASE : DLB2_DIR_PP_BASE)
> +
> +/**
> + * os_map_producer_port() - map a producer port into the caller's address
> space
> + * @hw: dlb2_hw handle for a particular device.
> + * @port_id: port ID
> + * @is_ldb: true for load-balanced port, false for a directed port
> + *
> + * This function maps the requested producer port memory into the caller's
> + * address space.
> + *
> + * Return:
> + * Returns the base address at which the PP memory was mapped, else NULL.
> + */
> +static inline void *os_map_producer_port(struct dlb2_hw *hw,
> + u8 port_id,
> + bool is_ldb)
> +{
> + uint64_t addr;
> + uint64_t pp_dma_base;
> +
> +
Nit: extra whitespace
[...]
> diff --git a/drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h
> b/drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h
> new file mode 100644
> index 0000000..7e48878
> --- /dev/null
> +++ b/drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h
> @@ -0,0 +1,447 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2016-2020 Intel Corporation
> + */
> +
> +#ifndef __DLB2_OSDEP_BITMAP_H
> +#define __DLB2_OSDEP_BITMAP_H
> +
> +#include <stdint.h>
> +#include <stdbool.h>
> +#include <stdio.h>
> +#include <unistd.h>
> +#include <rte_bitmap.h>
> +#include <rte_string_fns.h>
> +#include <rte_malloc.h>
> +#include <rte_errno.h>
> +#include "../dlb2_main.h"
> +
> +/*************************/
> +/*** Bitmap operations ***/
> +/*************************/
> +struct dlb2_bitmap {
> + struct rte_bitmap *map;
> + unsigned int len;
> +};
> +
> +/**
> + * dlb2_bitmap_alloc() - alloc a bitmap data structure
> + * @bitmap: pointer to dlb2_bitmap structure pointer.
> + * @len: number of entries in the bitmap.
> + *
> + * This function allocates a bitmap and initializes it with length @len. All
> + * entries are initially zero.
> + *
> + * Return:
> + * Returns 0 upon success, < 0 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or len is 0.
> + * ENOMEM - could not allocate memory for the bitmap data structure.
> + */
> +static inline int dlb2_bitmap_alloc(struct dlb2_bitmap **bitmap,
> + unsigned int len)
> +{
> + struct dlb2_bitmap *bm;
> + void *mem;
> + uint32_t alloc_size;
> + uint32_t nbits = (uint32_t)len;
> +
> + if (!bitmap || nbits == 0)
> + return -EINVAL;
> +
> + /* Allocate DLB2 bitmap control struct */
> + bm = rte_malloc("DLB2_PF",
> + sizeof(struct dlb2_bitmap),
> + RTE_CACHE_LINE_SIZE);
> +
> + if (!bm)
> + return -ENOMEM;
> +
> + /* Allocate bitmap memory */
> + alloc_size = rte_bitmap_get_memory_footprint(nbits);
> + mem = rte_malloc("DLB2_PF_BITMAP", alloc_size,
> RTE_CACHE_LINE_SIZE);
> + if (!mem) {
> + rte_free(bm);
> + return -ENOMEM;
> + }
> +
> + bm->map = rte_bitmap_init(len, mem, alloc_size);
> + if (!bm->map) {
> + rte_free(mem);
> + rte_free(bm);
> + return -ENOMEM;
> + }
> +
> + bm->len = len;
> +
> + *bitmap = bm;
> +
> + return 0;
> +}
> +
> +/**
> + * dlb2_bitmap_free() - free a previously allocated bitmap data structure
> + * @bitmap: pointer to dlb2_bitmap structure.
> + *
> + * This function frees a bitmap that was allocated with dlb2_bitmap_alloc().
> + */
> +static inline void dlb2_bitmap_free(struct dlb2_bitmap *bitmap)
> +{
> + if (!bitmap)
> + return;
> +
> + rte_free(bitmap->map);
> + rte_free(bitmap);
> +}
> +
> +/**
> + * dlb2_bitmap_fill() - fill a bitmap with all 1s
> + * @bitmap: pointer to dlb2_bitmap structure.
> + *
> + * This function sets all bitmap values to 1.
> + *
> + * Return:
> + * Returns 0 upon success, < 0 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or is uninitialized.
> + */
> +static inline int dlb2_bitmap_fill(struct dlb2_bitmap *bitmap)
> +{
> + unsigned int i;
> +
> + if (!bitmap || !bitmap->map)
> + return -EINVAL;
> +
> + /* TODO - optimize */
> + for (i = 0; i != bitmap->len; i++)
> + rte_bitmap_set(bitmap->map, i);
> +
> + return 0;
> +}
> +
> +/**
> + * dlb2_bitmap_fill() - fill a bitmap with all 0s
> + * @bitmap: pointer to dlb2_bitmap structure.
> + *
> + * This function sets all bitmap values to 0.
> + *
> + * Return:
> + * Returns 0 upon success, < 0 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or is uninitialized.
> + */
> +static inline int dlb2_bitmap_zero(struct dlb2_bitmap *bitmap)
> +{
> + if (!bitmap || !bitmap->map)
> + return -EINVAL;
> +
> + rte_bitmap_reset(bitmap->map);
> +
> + return 0;
> +}
> +
> +/**
> + * dlb2_bitmap_set() - set a bitmap entry
> + * @bitmap: pointer to dlb2_bitmap structure.
> + * @bit: bit index.
> + *
> + * Return:
> + * Returns 0 upon success, < 0 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or is uninitialized, or bit is larger than the
> + * bitmap length.
> + */
> +static inline int dlb2_bitmap_set(struct dlb2_bitmap *bitmap,
> + unsigned int bit)
> +{
> + if (!bitmap || !bitmap->map)
> + return -EINVAL;
> +
> + if (bitmap->len <= bit)
> + return -EINVAL;
> +
> + rte_bitmap_set(bitmap->map, bit);
> +
> + return 0;
> +}
> +
> +/**
> + * dlb2_bitmap_set_range() - set a range of bitmap entries
> + * @bitmap: pointer to dlb2_bitmap structure.
> + * @bit: starting bit index.
> + * @len: length of the range.
> + *
> + * Return:
> + * Returns 0 upon success, < 0 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or is uninitialized, or the range exceeds the
> bitmap
> + * length.
> + */
> +static inline int dlb2_bitmap_set_range(struct dlb2_bitmap *bitmap,
> + unsigned int bit,
> + unsigned int len)
> +{
> + unsigned int i;
> +
> + if (!bitmap || !bitmap->map)
> + return -EINVAL;
> +
> + if (bitmap->len <= bit)
> + return -EINVAL;
> +
> + /* TODO - optimize */
Leftover TODO
> + for (i = 0; i != len; i++)
> + rte_bitmap_set(bitmap->map, bit + i);
> +
> + return 0;
> +}
> +
> +/**
> + * dlb2_bitmap_clear() - clear a bitmap entry
> + * @bitmap: pointer to dlb2_bitmap structure.
> + * @bit: bit index.
> + *
> + * Return:
> + * Returns 0 upon success, < 0 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or is uninitialized, or bit is larger than the
> + * bitmap length.
> + */
> +static inline int dlb2_bitmap_clear(struct dlb2_bitmap *bitmap,
> + unsigned int bit)
> +{
> + if (!bitmap || !bitmap->map)
> + return -EINVAL;
> +
> + if (bitmap->len <= bit)
> + return -EINVAL;
> +
> + rte_bitmap_clear(bitmap->map, bit);
> +
> + return 0;
> +}
> +
> +/**
> + * dlb2_bitmap_clear_range() - clear a range of bitmap entries
> + * @bitmap: pointer to dlb2_bitmap structure.
> + * @bit: starting bit index.
> + * @len: length of the range.
> + *
> + * Return:
> + * Returns 0 upon success, < 0 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or is uninitialized, or the range exceeds the
> bitmap
> + * length.
> + */
> +static inline int dlb2_bitmap_clear_range(struct dlb2_bitmap *bitmap,
> + unsigned int bit,
> + unsigned int len)
> +{
> + unsigned int i;
> +
> + if (!bitmap || !bitmap->map)
> + return -EINVAL;
> +
> + if (bitmap->len <= bit)
> + return -EINVAL;
> +
> + /* TODO - optimize */
Leftover TODO
> + for (i = 0; i != len; i++)
> + rte_bitmap_clear(bitmap->map, bit + i);
> +
> + return 0;
> +}
> +
> +/**
> + * dlb2_bitmap_find_set_bit_range() - find an range of set bits
> + * @bitmap: pointer to dlb2_bitmap structure.
> + * @len: length of the range.
> + *
> + * This function looks for a range of set bits of length @len.
> + *
> + * Return:
> + * Returns the base bit index upon success, < 0 otherwise.
> + *
> + * Errors:
> + * ENOENT - unable to find a length *len* range of set bits.
> + * EINVAL - bitmap is NULL or is uninitialized, or len is invalid.
> + */
> +static inline int dlb2_bitmap_find_set_bit_range(struct dlb2_bitmap *bitmap,
> + unsigned int len)
> +{
> + unsigned int i, j = 0;
> +
> + if (!bitmap || !bitmap->map || len == 0)
> + return -EINVAL;
> +
> + if (bitmap->len < len)
> + return -ENOENT;
> +
> + /* TODO - optimize */
Leftover TODO
> + for (i = 0; i != bitmap->len; i++) {
> + if (rte_bitmap_get(bitmap->map, i)) {
> + if (++j == len)
> + return i - j + 1;
> + } else {
> + j = 0;
> + }
> + }
> +
> + /* No set bit range of length len? */
> + return -ENOENT;
> +}
> +
> +/**
> + * dlb2_bitmap_find_set_bit() - find an range of set bits
> + * @bitmap: pointer to dlb2_bitmap structure.
> + *
> + * This function looks for a single set bit.
> + *
> + * Return:
> + * Returns the base bit index upon success, -1 if not found, <-1 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or is uninitialized, or len is invalid.
> + */
> +static inline int dlb2_bitmap_find_set_bit(struct dlb2_bitmap *bitmap)
> +{
> + unsigned int i;
> +
> + if (!bitmap)
> + return -EINVAL;
> +
> + if (!bitmap->map)
> + return -EINVAL;
> +
> + /* TODO - optimize */
Leftover TODO
> + for (i = 0; i != bitmap->len; i++) {
> + if (rte_bitmap_get(bitmap->map, i))
> + return i;
> + }
> +
> + return -ENOENT;
> +}
> +
> +/**
> + * dlb2_bitmap_count() - returns the number of set bits
> + * @bitmap: pointer to dlb2_bitmap structure.
> + *
> + * This function looks for a single set bit.
> + *
> + * Return:
> + * Returns the number of set bits upon success, <0 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or is uninitialized.
> + */
> +static inline int dlb2_bitmap_count(struct dlb2_bitmap *bitmap)
> +{
> + int weight = 0;
> + unsigned int i;
> +
> + if (!bitmap)
> + return -EINVAL;
> +
> + if (!bitmap->map)
> + return -EINVAL;
> +
> + /* TODO - optimize */
Leftover TODO
> + for (i = 0; i != bitmap->len; i++) {
> + if (rte_bitmap_get(bitmap->map, i))
> + weight++;
> + }
> + return weight;
> +}
> +
> +/**
> + * dlb2_bitmap_longest_set_range() - returns longest contiguous range of set
> + * bits
> + * @bitmap: pointer to dlb2_bitmap structure.
> + *
> + * Return:
> + * Returns the bitmap's longest contiguous range of of set bits upon success,
> + * <0 otherwise.
> + *
> + * Errors:
> + * EINVAL - bitmap is NULL or is uninitialized.
> + */
> +static inline int dlb2_bitmap_longest_set_range(struct dlb2_bitmap *bitmap)
> +{
> + int max_len = 0, len = 0;
> + unsigned int i;
> +
> + if (!bitmap)
> + return -EINVAL;
> +
> + if (!bitmap->map)
> + return -EINVAL;
> +
> + /* TODO - optimize */
Leftover TODO
[...]
> diff --git a/drivers/event/dlb2/pf/dlb2_main.c
> b/drivers/event/dlb2/pf/dlb2_main.c
> new file mode 100644
> index 0000000..1c275ff
> --- /dev/null
> +++ b/drivers/event/dlb2/pf/dlb2_main.c
> @@ -0,0 +1,620 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2016-2020 Intel Corporation
> + */
> +
> +#include <stdint.h>
> +#include <stdbool.h>
> +#include <stdio.h>
> +#include <errno.h>
> +#include <assert.h>
> +#include <unistd.h>
> +#include <string.h>
> +
> +#include <rte_malloc.h>
> +#include <rte_errno.h>
> +
> +#include "base/dlb2_resource.h"
> +#include "base/dlb2_osdep.h"
> +#include "base/dlb2_regs.h"
> +#include "dlb2_main.h"
> +#include "../dlb2_user.h"
> +#include "../dlb2_priv.h"
> +#include "../dlb2_iface.h"
> +#include "../dlb2_inline_fns.h"
> +
> +#define PF_ID_ZERO 0 /* PF ONLY! */
> +#define NO_OWNER_VF 0 /* PF ONLY! */
> +#define NOT_VF_REQ false /* PF ONLY! */
> +
> +#define DLB2_PCI_CFG_SPACE_SIZE 256
> +#define DLB2_PCI_CAP_POINTER 0x34
> +#define DLB2_PCI_CAP_NEXT(hdr) (((hdr) >> 8) & 0xFC)
> +#define DLB2_PCI_CAP_ID(hdr) ((hdr) & 0xFF)
> +#define DLB2_PCI_EXT_CAP_NEXT(hdr) (((hdr) >> 20) & 0xFFC)
> +#define DLB2_PCI_EXT_CAP_ID(hdr) ((hdr) & 0xFFFF)
> +#define DLB2_PCI_EXT_CAP_ID_ERR 1
> +#define DLB2_PCI_ERR_UNCOR_MASK 8
> +#define DLB2_PCI_ERR_UNC_UNSUP 0x00100000
> +
> +#define DLB2_PCI_EXP_DEVCTL 8
> +#define DLB2_PCI_LNKCTL 16
> +#define DLB2_PCI_SLTCTL 24
> +#define DLB2_PCI_RTCTL 28
> +#define DLB2_PCI_EXP_DEVCTL2 40
> +#define DLB2_PCI_LNKCTL2 48
> +#define DLB2_PCI_SLTCTL2 56
> +#define DLB2_PCI_CMD 4
> +#define DLB2_PCI_X_CMD 2
> +#define DLB2_PCI_EXP_DEVSTA 10
> +#define DLB2_PCI_EXP_DEVSTA_TRPND 0x20
> +#define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000
> +
> +#define DLB2_PCI_CAP_ID_EXP 0x10
> +#define DLB2_PCI_CAP_ID_MSIX 0x11
> +#define DLB2_PCI_EXT_CAP_ID_PAS 0x1B
> +#define DLB2_PCI_EXT_CAP_ID_PRI 0x13
> +#define DLB2_PCI_EXT_CAP_ID_ACS 0xD
> +
> +#define DLB2_PCI_PRI_CTRL_ENABLE 0x1
> +#define DLB2_PCI_PRI_ALLOC_REQ 0xC
> +#define DLB2_PCI_PRI_CTRL 0x4
> +#define DLB2_PCI_MSIX_FLAGS 0x2
> +#define DLB2_PCI_MSIX_FLAGS_ENABLE 0x8000
> +#define DLB2_PCI_MSIX_FLAGS_MASKALL 0x4000
> +#define DLB2_PCI_ERR_ROOT_STATUS 0x30
> +#define DLB2_PCI_ERR_COR_STATUS 0x10
> +#define DLB2_PCI_ERR_UNCOR_STATUS 0x4
> +#define DLB2_PCI_COMMAND_INTX_DISABLE 0x400
> +#define DLB2_PCI_ACS_CAP 0x4
> +#define DLB2_PCI_ACS_CTRL 0x6
> +#define DLB2_PCI_ACS_SV 0x1
> +#define DLB2_PCI_ACS_RR 0x4
> +#define DLB2_PCI_ACS_CR 0x8
> +#define DLB2_PCI_ACS_UF 0x10
> +#define DLB2_PCI_ACS_EC 0x20
> +
> +static int
> +dlb2_pci_find_ext_capability(struct rte_pci_device *pdev, uint32_t id)
> +{
> + uint32_t hdr;
> + size_t sz;
> + int pos;
> +
> + pos = DLB2_PCI_CFG_SPACE_SIZE;
> + sz = sizeof(hdr);
> +
> + while (pos > 0xFF) {
> + if (rte_pci_read_config(pdev, &hdr, sz, pos) != (int)sz)
> + return -1;
> +
> + if (DLB2_PCI_EXT_CAP_ID(hdr) == id)
> + return pos;
> +
> + pos = DLB2_PCI_EXT_CAP_NEXT(hdr);
> + }
> +
> + return -1;
> +}
> +
> +static int dlb2_pci_find_capability(struct rte_pci_device *pdev, uint32_t id)
> +{
> + uint8_t pos;
> + int ret;
> + uint16_t hdr;
> +
> + ret = rte_pci_read_config(pdev, &pos, 1, DLB2_PCI_CAP_POINTER);
> + pos &= 0xFC;
> +
> + if (ret != 1)
> + return -1;
> +
> + while (pos > 0x3F) {
> + ret = rte_pci_read_config(pdev, &hdr, 2, pos);
> + if (ret != 2)
> + return -1;
> +
> + if (DLB2_PCI_CAP_ID(hdr) == id)
> + return pos;
> +
> + if (DLB2_PCI_CAP_ID(hdr) == 0xFF)
> + return -1;
> +
> + pos = DLB2_PCI_CAP_NEXT(hdr);
> + }
> +
> + return -1;
> +}
> +
> +static int
> +dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev)
> +{
> + int i;
> +
> + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_MOVDIR64B))
> + dlb2_dev->enqueue_four = dlb2_movdir64b;
> + else
> + dlb2_dev->enqueue_four = dlb2_movntdq;
> +
> + /* Initialize software state */
> + for (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++)
> + dlb2_list_init_head(&dlb2_dev->ldb_port_pages[i].list);
> +
> + for (i = 0; i < DLB2_MAX_NUM_DIR_PORTS; i++)
> + dlb2_list_init_head(&dlb2_dev->dir_port_pages[i].list);
> +
> + rte_spinlock_init(&dlb2_dev->resource_mutex);
> + rte_spinlock_init(&dlb2_dev->measurement_lock);
> +
> + return 0;
> +}
> +
> +static void dlb2_pf_enable_pm(struct dlb2_dev *dlb2_dev)
> +{
> + dlb2_clr_pmcsr_disable(&dlb2_dev->hw);
> +}
> +
> +#define DLB2_READY_RETRY_LIMIT 1000
> +static int dlb2_pf_wait_for_device_ready(struct dlb2_dev *dlb2_dev)
> +{
> + u32 retries = 0;
> +
> + /* Allow at least 1s for the device to become active after power-on */
> + for (retries = 0; retries < DLB2_READY_RETRY_LIMIT; retries++) {
> + union dlb2_cfg_mstr_cfg_diagnostic_idle_status idle;
> + union dlb2_cfg_mstr_cfg_pm_status pm_st;
> + u32 addr;
> +
> + addr = DLB2_CFG_MSTR_CFG_PM_STATUS;
> + pm_st.val = DLB2_CSR_RD(&dlb2_dev->hw, addr);
> + addr = DLB2_CFG_MSTR_CFG_DIAGNOSTIC_IDLE_STATUS;
> + idle.val = DLB2_CSR_RD(&dlb2_dev->hw, addr);
> + if (pm_st.field.pmsm == 1 && idle.field.dlb_func_idle == 1)
> + break;
> +
> + rte_delay_ms(1);
> + };
> +
> + if (retries == DLB2_READY_RETRY_LIMIT) {
> + printf("[%s()] wait for device ready timed out\n",
> + __func__);
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> +struct dlb2_dev *
> +dlb2_probe(struct rte_pci_device *pdev)
> +{
> + struct dlb2_dev *dlb2_dev;
> + int ret = 0;
> +
> + DLB2_INFO(dlb2_dev, "probe\n");
> +
> + dlb2_dev = rte_malloc("DLB2_PF", sizeof(struct dlb2_dev),
> + RTE_CACHE_LINE_SIZE);
> +
> + if (!dlb2_dev) {
> + ret = -ENOMEM;
> + goto dlb2_dev_malloc_fail;
> + }
> +
> + /* PCI Bus driver has already mapped bar space into process.
> + * Save off our IO register and FUNC addresses.
> + */
> +
> + /* BAR 0 */
> + if (pdev->mem_resource[0].addr == NULL) {
> + DLB2_ERR(dlb2_dev, "probe: BAR 0 addr (csr_kva) is NULL\n");
> + ret = -EINVAL;
> + goto pci_mmap_bad_addr;
> + }
> + dlb2_dev->hw.func_kva = (void *)(uintptr_t)pdev-
> >mem_resource[0].addr;
> + dlb2_dev->hw.func_phys_addr = pdev->mem_resource[0].phys_addr;
> +
> + DLB2_INFO(dlb2_dev, "DLB2 FUNC VA=%p, PA=%p, len=%p\n",
> + (void *)dlb2_dev->hw.func_kva,
> + (void *)dlb2_dev->hw.func_phys_addr,
> + (void *)(pdev->mem_resource[0].len));
> +
> + /* BAR 2 */
> + if (pdev->mem_resource[2].addr == NULL) {
> + DLB2_ERR(dlb2_dev, "probe: BAR 2 addr (func_kva) is NULL\n");
> + ret = -EINVAL;
> + goto pci_mmap_bad_addr;
> + }
> + dlb2_dev->hw.csr_kva = (void *)(uintptr_t)pdev-
> >mem_resource[2].addr;
> + dlb2_dev->hw.csr_phys_addr = pdev->mem_resource[2].phys_addr;
> +
> + DLB2_INFO(dlb2_dev, "DLB2 CSR VA=%p, PA=%p, len=%p\n",
> + (void *)dlb2_dev->hw.csr_kva,
> + (void *)dlb2_dev->hw.csr_phys_addr,
> + (void *)(pdev->mem_resource[2].len));
> +
> + dlb2_dev->pdev = pdev;
> +
> + /* PM enable must be done before any other MMIO accesses, and this
> + * setting is persistent across device reset.
> + */
> + dlb2_pf_enable_pm(dlb2_dev);
> +
> + ret = dlb2_pf_wait_for_device_ready(dlb2_dev);
> + if (ret)
> + goto wait_for_device_ready_fail;
> +
> + ret = dlb2_pf_reset(dlb2_dev);
> + if (ret)
> + goto dlb2_reset_fail;
> +
> + ret = dlb2_pf_init_driver_state(dlb2_dev);
> + if (ret)
> + goto init_driver_state_fail;
> +
> + ret = dlb2_resource_init(&dlb2_dev->hw);
> + if (ret)
> + goto resource_init_fail;
> +
> + return dlb2_dev;
> +
> +resource_init_fail:
> + dlb2_resource_free(&dlb2_dev->hw);
> +init_driver_state_fail:
> +dlb2_reset_fail:
> +pci_mmap_bad_addr:
> +wait_for_device_ready_fail:
> + rte_free(dlb2_dev);
> +dlb2_dev_malloc_fail:
> + rte_errno = ret;
> + return NULL;
> +}
> +
> +int
> +dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
> +{
> + int ret = 0;
> + int i = 0;
> + uint32_t dword[16];
> + uint16_t cmd;
> + off_t off;
> +
> + uint16_t dev_ctl_word;
> + uint16_t dev_ctl2_word;
> + uint16_t lnk_word;
> + uint16_t lnk_word2;
> + uint16_t slt_word;
> + uint16_t slt_word2;
> + uint16_t rt_ctl_word;
> + uint32_t pri_reqs_dword;
> + uint16_t pri_ctrl_word;
> +
> + int pcie_cap_offset;
> + int pri_cap_offset;
> + int msix_cap_offset;
> + int err_cap_offset;
> + int acs_cap_offset;
> + int wait_count;
> +
> + uint16_t devsta_busy_word;
> + uint16_t devctl_word;
> +
> + struct rte_pci_device *pdev = dlb2_dev->pdev;
> +
> + /* Save PCI config state */
> +
> + for (i = 0; i < 16; i++) {
> + if (rte_pci_read_config(pdev, &dword[i], 4, i * 4) != 4)
> + return ret;
> + }
> +
> + pcie_cap_offset = dlb2_pci_find_capability(pdev,
> DLB2_PCI_CAP_ID_EXP);
> +
> + if (pcie_cap_offset < 0) {
> + printf("[%s()] failed to find the pcie capability\n",
> + __func__);
> + return pcie_cap_offset;
> + }
> +
> + off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL;
> + if (rte_pci_read_config(pdev, &dev_ctl_word, 2, off) != 2)
> + dev_ctl_word = 0;
> +
> + off = pcie_cap_offset + DLB2_PCI_LNKCTL;
> + if (rte_pci_read_config(pdev, &lnk_word, 2, off) != 2)
> + lnk_word = 0;
> +
> + off = pcie_cap_offset + DLB2_PCI_SLTCTL;
> + if (rte_pci_read_config(pdev, &slt_word, 2, off) != 2)
> + slt_word = 0;
> +
> + off = pcie_cap_offset + DLB2_PCI_RTCTL;
> + if (rte_pci_read_config(pdev, &rt_ctl_word, 2, off) != 2)
> + rt_ctl_word = 0;
> +
> + off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL2;
> + if (rte_pci_read_config(pdev, &dev_ctl2_word, 2, off) != 2)
> + dev_ctl2_word = 0;
> +
> + off = pcie_cap_offset + DLB2_PCI_LNKCTL2;
> + if (rte_pci_read_config(pdev, &lnk_word2, 2, off) != 2)
> + lnk_word2 = 0;
> +
> + off = pcie_cap_offset + DLB2_PCI_SLTCTL2;
> + if (rte_pci_read_config(pdev, &slt_word2, 2, off) != 2)
> + slt_word2 = 0;
> +
> + off = DLB2_PCI_EXT_CAP_ID_PRI;
> + pri_cap_offset = dlb2_pci_find_ext_capability(pdev, off);
> +
> + if (pri_cap_offset >= 0) {
> + off = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ;
> + if (rte_pci_read_config(pdev, &pri_reqs_dword, 4, off) != 4)
> + pri_reqs_dword = 0;
> + }
> +
> + /* clear the PCI command register before issuing the FLR */
> +
> + off = DLB2_PCI_CMD;
> + cmd = 0;
> + if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
> + printf("[%s()] failed to write the pci command\n",
> + __func__);
> + return ret;
> + }
> +
> + /* issue the FLR */
> + for (wait_count = 0; wait_count < 4; wait_count++) {
> + int sleep_time;
> +
> + off = pcie_cap_offset + DLB2_PCI_EXP_DEVSTA;
> + ret = rte_pci_read_config(pdev, &devsta_busy_word, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to read the pci device status\n",
> + __func__);
> + return ret;
> + }
> +
> + if (!(devsta_busy_word & DLB2_PCI_EXP_DEVSTA_TRPND))
> + break;
> +
> + sleep_time = (1 << (wait_count)) * 100;
> + rte_delay_ms(sleep_time);
> + }
> +
> + if (wait_count == 4) {
> + printf("[%s()] wait for pci pending transactions timed out\n",
> + __func__);
> + return -1;
> + }
> +
> + off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL;
> + ret = rte_pci_read_config(pdev, &devctl_word, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to read the pcie device control\n",
> + __func__);
> + return ret;
> + }
> +
> + devctl_word |= DLB2_PCI_EXP_DEVCTL_BCR_FLR;
> +
> + ret = rte_pci_write_config(pdev, &devctl_word, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie device control\n",
> + __func__);
> + return ret;
> + }
> +
> + rte_delay_ms(100);
> +
> + /* Restore PCI config state */
> +
> + if (pcie_cap_offset >= 0) {
> + off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL;
> + ret = rte_pci_write_config(pdev, &dev_ctl_word, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie device control
> at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = pcie_cap_offset + DLB2_PCI_LNKCTL;
> + ret = rte_pci_write_config(pdev, &lnk_word, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = pcie_cap_offset + DLB2_PCI_SLTCTL;
> + ret = rte_pci_write_config(pdev, &slt_word, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = pcie_cap_offset + DLB2_PCI_RTCTL;
> + ret = rte_pci_write_config(pdev, &rt_ctl_word, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL2;
> + ret = rte_pci_write_config(pdev, &dev_ctl2_word, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = pcie_cap_offset + DLB2_PCI_LNKCTL2;
> + ret = rte_pci_write_config(pdev, &lnk_word2, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = pcie_cap_offset + DLB2_PCI_SLTCTL2;
> + ret = rte_pci_write_config(pdev, &slt_word2, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> + }
> +
> + if (pri_cap_offset >= 0) {
> + pri_ctrl_word = DLB2_PCI_PRI_CTRL_ENABLE;
> +
> + off = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ;
> + ret = rte_pci_write_config(pdev, &pri_reqs_dword, 4, off);
> + if (ret != 4) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = pri_cap_offset + DLB2_PCI_PRI_CTRL;
> + ret = rte_pci_write_config(pdev, &pri_ctrl_word, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> + }
> +
> + off = DLB2_PCI_EXT_CAP_ID_ERR;
> + err_cap_offset = dlb2_pci_find_ext_capability(pdev, off);
> +
> + if (err_cap_offset >= 0) {
> + uint32_t tmp;
> +
> + off = err_cap_offset + DLB2_PCI_ERR_ROOT_STATUS;
> + if (rte_pci_read_config(pdev, &tmp, 4, off) != 4)
> + tmp = 0;
> +
> + ret = rte_pci_write_config(pdev, &tmp, 4, off);
> + if (ret != 4) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = err_cap_offset + DLB2_PCI_ERR_COR_STATUS;
> + if (rte_pci_read_config(pdev, &tmp, 4, off) != 4)
> + tmp = 0;
> +
> + ret = rte_pci_write_config(pdev, &tmp, 4, off);
> + if (ret != 4) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = err_cap_offset + DLB2_PCI_ERR_UNCOR_STATUS;
> + if (rte_pci_read_config(pdev, &tmp, 4, off) != 4)
> + tmp = 0;
> +
> + ret = rte_pci_write_config(pdev, &tmp, 4, off);
> + if (ret != 4) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> + }
> +
> + for (i = 16; i > 0; i--) {
> + off = (i - 1) * 4;
> + ret = rte_pci_write_config(pdev, &dword[i - 1], 4, off);
> + if (ret != 4) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> + }
> +
> + off = DLB2_PCI_CMD;
> + if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {
> + cmd &= ~DLB2_PCI_COMMAND_INTX_DISABLE;
> + if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
> + printf("[%s()] failed to write the pci command\n",
> + __func__);
> + return ret;
> + }
> + }
> +
> + msix_cap_offset = dlb2_pci_find_capability(pdev,
> + DLB2_PCI_CAP_ID_MSIX);
> + if (msix_cap_offset >= 0) {
> + off = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;
> + if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {
> + cmd |= DLB2_PCI_MSIX_FLAGS_ENABLE;
> + cmd |= DLB2_PCI_MSIX_FLAGS_MASKALL;
> + if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
> + printf("[%s()] failed to write msix flags\n",
> + __func__);
> + return ret;
> + }
> + }
> +
> + off = msix_cap_offset + DLB2_PCI_MSIX_FLAGS;
> + if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) {
> + cmd &= ~DLB2_PCI_MSIX_FLAGS_MASKALL;
> + if (rte_pci_write_config(pdev, &cmd, 2, off) != 2) {
> + printf("[%s()] failed to write msix flags\n",
> + __func__);
> + return ret;
> + }
> + }
> + }
> +
> + off = DLB2_PCI_EXT_CAP_ID_ACS;
> + acs_cap_offset = dlb2_pci_find_ext_capability(pdev, off);
> +
> + if (acs_cap_offset >= 0) {
> + uint16_t acs_cap, acs_ctrl, acs_mask;
> + off = acs_cap_offset + DLB2_PCI_ACS_CAP;
> + if (rte_pci_read_config(pdev, &acs_cap, 2, off) != 2)
> + acs_cap = 0;
> +
> + off = acs_cap_offset + DLB2_PCI_ACS_CTRL;
> + if (rte_pci_read_config(pdev, &acs_ctrl, 2, off) != 2)
> + acs_ctrl = 0;
> +
> + acs_mask = DLB2_PCI_ACS_SV | DLB2_PCI_ACS_RR;
> + acs_mask |= (DLB2_PCI_ACS_CR | DLB2_PCI_ACS_UF);
> + acs_ctrl |= (acs_cap & acs_mask);
> +
> + ret = rte_pci_write_config(pdev, &acs_ctrl, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> +
> + off = acs_cap_offset + DLB2_PCI_ACS_CTRL;
> + if (rte_pci_read_config(pdev, &acs_ctrl, 2, off) != 2)
> + acs_ctrl = 0;
> +
> + acs_mask = DLB2_PCI_ACS_RR | DLB2_PCI_ACS_CR;
> + acs_mask |= DLB2_PCI_ACS_EC;
> + acs_ctrl &= ~acs_mask;
> +
> + off = acs_cap_offset + DLB2_PCI_ACS_CTRL;
> + ret = rte_pci_write_config(pdev, &acs_ctrl, 2, off);
> + if (ret != 2) {
> + printf("[%s()] failed to write the pcie config space at
> offset %d\n",
> + __func__, (int)off);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
Since this PCIe function-level reset code is more PCIe-specific than the other
functions
in this file, what do you think about putting code this PCIe function-level
reset code in
its own file, e.g. dlb2_pci.c? Just a thought.
> +
> +/**********************************/
> +/****** Device configuration ******/
> +/**********************************/
> +
Nit: this comment block would make more sense in patch 8 when the first device
configuration functions are added.
> diff --git a/drivers/event/dlb2/pf/dlb2_main.h
> b/drivers/event/dlb2/pf/dlb2_main.h
> new file mode 100644
> index 0000000..a914077
> --- /dev/null
> +++ b/drivers/event/dlb2/pf/dlb2_main.h
> @@ -0,0 +1,107 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2016-2020 Intel Corporation
> + */
> +
> +#ifndef __DLB2_MAIN_H
> +#define __DLB2_MAIN_H
> +
> +#include <rte_debug.h>
> +#include <rte_log.h>
> +#include <rte_spinlock.h>
> +#include <rte_pci.h>
> +#include <rte_bus_pci.h>
> +
> +#ifndef PAGE_SIZE
> +#define PAGE_SIZE (sysconf(_SC_PAGESIZE))
> +#endif
> +
> +#include "base/dlb2_hw_types.h"
> +#include "../dlb2_user.h"
> +
> +#define DLB2_DEFAULT_UNREGISTER_TIMEOUT_S 5
> +
> +struct dlb2_dev;
> +
> +struct dlb2_port_memory {
> + struct dlb2_list_head list;
> + void *cq_base;
> + bool valid;
> +};
> +
> +struct dlb2_dev {
> + struct rte_pci_device *pdev;
> + struct dlb2_hw hw;
> + /* struct list_head list; */
> + struct device *dlb2_device;
> + struct dlb2_port_memory
> ldb_port_pages[DLB2_MAX_NUM_LDB_PORTS];
> + struct dlb2_port_memory
> dir_port_pages[DLB2_MAX_NUM_DIR_PORTS];
> + /* The enqueue_four function enqueues four HCWs (one cache-line
> worth)
> + * to the DLB2, using whichever mechanism is supported by the platform
> + * on which this driver is running.
> + */
> + void (*enqueue_four)(void *qe4, void *pp_addr);
> +
> + bool domain_reset_failed;
> + /* The resource mutex serializes access to driver data structures and
> + * hardware registers.
> + */
> + rte_spinlock_t resource_mutex;
> + rte_spinlock_t measurement_lock;
> + bool worker_launched;
> + u8 revision;
> +};
> +
> +struct dlb2_dev *dlb2_probe(struct rte_pci_device *pdev);
> +
> +/* The following functions were pf_ops in kernel driver implementation */
Probably not important for the DPDK implementation...and better to avoid
mentioning the kernel implementation to avoid any appearance of licensing
impropriety.
> +int dlb2_pf_reset(struct dlb2_dev *dlb2_dev);
> +int dlb2_pf_create_sched_domain(struct dlb2_hw *hw,
> + struct dlb2_create_sched_domain_args *args,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_create_ldb_queue(struct dlb2_hw *hw,
> + u32 domain_id,
> + struct dlb2_create_ldb_queue_args *args,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_create_dir_queue(struct dlb2_hw *hw,
> + u32 domain_id,
> + struct dlb2_create_dir_queue_args *args,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_create_ldb_port(struct dlb2_hw *hw,
> + u32 domain_id,
> + struct dlb2_create_ldb_port_args *args,
> + uintptr_t cq_dma_base,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_create_dir_port(struct dlb2_hw *hw,
> + u32 domain_id,
> + struct dlb2_create_dir_port_args *args,
> + uintptr_t cq_dma_base,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_start_domain(struct dlb2_hw *hw,
> + u32 domain_id,
> + struct dlb2_start_domain_args *args,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_enable_ldb_port(struct dlb2_hw *hw,
> + u32 domain_id,
> + struct dlb2_enable_ldb_port_args *args,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_disable_ldb_port(struct dlb2_hw *hw,
> + u32 domain_id,
> + struct dlb2_disable_ldb_port_args *args,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_enable_dir_port(struct dlb2_hw *hw,
> + u32 domain_id,
> + struct dlb2_enable_dir_port_args *args,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_disable_dir_port(struct dlb2_hw *hw,
> + u32 domain_id,
> + struct dlb2_disable_dir_port_args *args,
> + struct dlb2_cmd_response *resp);
> +int dlb2_pf_reset_domain(struct dlb2_hw *hw, u32 domain_id);
> +int dlb2_pf_ldb_port_owned_by_domain(struct dlb2_hw *hw,
> + u32 domain_id,
> + u32 port_id);
> +int dlb2_pf_dir_port_owned_by_domain(struct dlb2_hw *hw,
> + u32 domain_id,
> + u32 port_id);
> +
> +#endif /* __DLB2_MAIN_H */
> diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c
> new file mode 100644
> index 0000000..8c5ec20
> --- /dev/null
> +++ b/drivers/event/dlb2/pf/dlb2_pf.c
> @@ -0,0 +1,251 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2016-2020 Intel Corporation
> + */
> +
> +#include <stdint.h>
> +#include <stdbool.h>
> +#include <stdio.h>
> +#include <sys/mman.h>
> +#include <sys/fcntl.h>
> +#include <sys/time.h>
> +#include <errno.h>
> +#include <assert.h>
> +#include <unistd.h>
> +#include <string.h>
> +#include <rte_debug.h>
> +#include <rte_log.h>
> +#include <rte_dev.h>
> +#include <rte_devargs.h>
> +#include <rte_mbuf.h>
> +#include <rte_ring.h>
> +#include <rte_errno.h>
> +#include <rte_kvargs.h>
> +#include <rte_malloc.h>
> +#include <rte_cycles.h>
> +#include <rte_io.h>
> +#include <rte_pci.h>
> +#include <rte_bus_pci.h>
> +#include <rte_eventdev.h>
> +#include <rte_eventdev_pmd.h>
> +#include <rte_eventdev_pmd_pci.h>
> +#include <rte_memory.h>
> +#include <rte_string_fns.h>
> +
> +#include "../dlb2_priv.h"
> +#include "../dlb2_iface.h"
> +#include "../dlb2_inline_fns.h"
> +#include "dlb2_main.h"
> +#include "base/dlb2_hw_types.h"
> +#include "base/dlb2_osdep.h"
> +#include "base/dlb2_resource.h"
> +
> +extern struct dlb2_dev *dlb2_probe(struct rte_pci_device *pdev);
Not needed, dlb2_probe is declared in pf/dlb2_main.h
> +
> +#if !defined RTE_ARCH_X86_64
> +#error "This implementation only supports RTE_ARCH_X86_64 architecture."
> +#endif
> +
Seems redundant, this is checked in dlb2.c and meson.build should ensure it's
not
built for other archs anyway.
[...]
> +static void
> +dlb2_pf_iface_fn_ptrs_init(void)
> +{
> +
Nit: extra whitespace
Thanks,
Gage
