On 30-Sep-20 3:59 PM, 谢华伟(此时此刻） wrote:
From c13f981e287254cd0877cc7b98ee2dd7b80c3b69 Mon Sep 17 00:00:00 2001
From: "huawei.xhw" <huawei....@alibaba-inc.com>
Date: Wed, 30 Sep 2020 22:37:03 +0800
Subject: [PATCH v2] pci: support both PIO and MMIO BAR for legacy
virtio on
x86
Legacy virtio-pci only supports PIO BAR resource. As we need to create
lots of
virtio devices and PIO resource on x86 is very limited, we expose MMIO BAR.
Kernel supports both PIO and MMIO BAR for legacy virtio-pci device. We
handles
different type of BAR in the similar way.
In previous implementation, with igb_uio we get PIO address from igb_uio
sysfs entry; with uio_pci_generic, we get PIO address from
/proc/ioports.
For PIO/MMIO RW, there is different path for different drivers and arch.
For VFIO, PIO/MMIO RW is through syscall, which has big performance
issue.
On X86, it assumes only PIO is supported.
All of the above is too much twisted.
This patch unifies the way to get both PIO and MMIO address for
different driver
and arch, all from standard resource attr under pci sysfs.
We distinguish PIO and MMIO by their address like how kernel does. It is
ugly but works.
Signed-off-by: huawei.xhw <huawei....@alibaba-inc.com>
---
You patches are somehow malformed (at least according to my inline diff
viewer). Are you using git-send-email to send patches?
--
Thanks,
Anatoly
